Zachary W. Wilkes

Array ( [id] => 17032806 [patent_doc_number] => 11094624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Semiconductor device having capacitor [patent_app_type] => utility [patent_app_number] => 16/596074 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 6352 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16752624 [patent_doc_number] => 20210104636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => NONSTOICHIOMETRIC STRUCTURES WITH MULTIPLE CONTROLLED BANDGAP ENERGY LEVELS AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/596150 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17758272 [patent_doc_number] => 11398571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Devices and electronic systems including vertical transistors, and related methods [patent_app_type] => utility [patent_app_number] => 16/596117 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 11521 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15776273 [patent_doc_number] => 20200119154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/596212 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 1 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15443195 [patent_doc_number] => 20200035781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SEMICONDUCTOR DEVICE WITH SUPPORT PATTERN [patent_app_type] => utility [patent_app_number] => 16/593438 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16245932 [patent_doc_number] => 10745271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Method for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices using a flat surface above a sacrificial layer [patent_app_type] => utility [patent_app_number] => 16/587274 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 44 [patent_no_of_words] => 9980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15504011 [patent_doc_number] => 20200052194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => MAGNETORESISTANCE EFFECT ELEMENT [patent_app_type] => utility [patent_app_number] => 16/587178 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16487892 [patent_doc_number] => 20200381501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => DOUBLE-SIDED DISPLAY PANEL, FABRICATING METHOD OF SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/605211 [patent_app_country] => US [patent_app_date] => 2019-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17239639 [patent_doc_number] => 11183531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Display screen, display module, and terminal [patent_app_type] => utility [patent_app_number] => 16/584207 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4920 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16846163 [patent_doc_number] => 11018260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Non-volatile memory device with reduced area [patent_app_type] => utility [patent_app_number] => 16/573803 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16715685 [patent_doc_number] => 20210082832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof [patent_app_type] => utility [patent_app_number] => 16/573817 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17092880 [patent_doc_number] => 11121078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => SRAM having irregularly shaped metal lines [patent_app_type] => utility [patent_app_number] => 16/573769 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17623167 [patent_doc_number] => 11342231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Integrated circuit device with low threshold voltage [patent_app_type] => utility [patent_app_number] => 16/573866 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16684548 [patent_doc_number] => 10944041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Hybrid ultrasonic transducer and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/573833 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 10096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16594089 [patent_doc_number] => 10903366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-26 [patent_title] => Forming fin-FET semiconductor structures [patent_app_type] => utility [patent_app_number] => 16/573888 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15745831 [patent_doc_number] => 20200111805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => Method of ONO Stack Formation [patent_app_type] => utility [patent_app_number] => 16/572463 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18016542 [patent_doc_number] => 11508850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/271716 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 73 [patent_no_of_words] => 40315 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17271716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16332018 [patent_doc_number] => 20200302984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => MAGNETIC DEVICE AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/557802 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16677451 [patent_doc_number] => 20210066217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR MAKING [patent_app_type] => utility [patent_app_number] => 16/557825 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16820024 [patent_doc_number] => 11004863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Non-volatile memory with gate all around thin film transistor and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/557803 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5586 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557803 [rel_patent_id] =>[rel_patent_doc_number] =>)