Search

Zachary W. Wilkes

Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
1061
Issued Applications
667
Pending Applications
96
Abandoned Applications
322

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19392860 [patent_doc_number] => 20240282730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => INTEGRATED CIRCUITS WITH SELECTABLE PACKAGING TYPES [patent_app_type] => utility [patent_app_number] => 18/441462 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441462 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441462
INTEGRATED CIRCUITS WITH SELECTABLE PACKAGING TYPES Feb 13, 2024 Pending
Array ( [id] => 19928316 [patent_doc_number] => 12302627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor device with non-conformal gate dielectric layers [patent_app_type] => utility [patent_app_number] => 18/441443 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441443
Semiconductor device with non-conformal gate dielectric layers Feb 13, 2024 Issued
Array ( [id] => 19221479 [patent_doc_number] => 20240186183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/441520 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441520
Field effect transistor including channels having a hollow closed cross-sectional structure and method of manufacturing the same Feb 13, 2024 Issued
Array ( [id] => 20119644 [patent_doc_number] => 12369383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor structure with gate-all-around devices and stacked FinFET devices [patent_app_type] => utility [patent_app_number] => 18/438632 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438632
Semiconductor structure with gate-all-around devices and stacked FinFET devices Feb 11, 2024 Issued
Array ( [id] => 19886875 [patent_doc_number] => 12272604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Integrated circuit device with low threshold voltage [patent_app_type] => utility [patent_app_number] => 18/439362 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439362 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439362
Integrated circuit device with low threshold voltage Feb 11, 2024 Issued
Array ( [id] => 19288033 [patent_doc_number] => 20240224516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => STRING DRIVER ASSEMBLIES INCLUDING TWO-DIMENSIONAL MATERIALS, AND RELATED MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/439662 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439662
String driver assemblies including two-dimensional materials, and related memory devices Feb 11, 2024 Issued
Array ( [id] => 19873705 [patent_doc_number] => 12266575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/432251 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432251 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432251
Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same Feb 4, 2024 Issued
Array ( [id] => 19206358 [patent_doc_number] => 20240178257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH IMAGE SENSORS AND WAFER BONDING [patent_app_type] => utility [patent_app_number] => 18/432035 [patent_app_country] => US [patent_app_date] => 2024-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432035
Multilevel semiconductor device and structure with image sensors and wafer bonding Feb 3, 2024 Issued
Array ( [id] => 19470670 [patent_doc_number] => 20240324340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/431553 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431553 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431553
DISPLAY APPARATUS Feb 1, 2024 Pending
Array ( [id] => 19873656 [patent_doc_number] => 12266525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Photomask pellicle including network of nanowires and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/426387 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 7768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426387
Photomask pellicle including network of nanowires and method of forming the same Jan 29, 2024 Issued
Array ( [id] => 19704937 [patent_doc_number] => 12198984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Semiconductor device including gate spacer with tilted portion and method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/426852 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426852
Semiconductor device including gate spacer with tilted portion and method of manufacturing thereof Jan 29, 2024 Issued
Array ( [id] => 19952820 [patent_doc_number] => 12324208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Method for manufacturing semiconductor device including annealing treatment of inner spacer layer [patent_app_type] => utility [patent_app_number] => 18/425058 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 6951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425058
Method for manufacturing semiconductor device including annealing treatment of inner spacer layer Jan 28, 2024 Issued
Array ( [id] => 19255260 [patent_doc_number] => 20240206257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => ORGANIC LIGHT EMITTING DIODE DISPLAY [patent_app_type] => utility [patent_app_number] => 18/419083 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419083
Organic light emitting diode display including plurality of pixels, storage capacitor, and wiring lines Jan 21, 2024 Issued
Array ( [id] => 19161257 [patent_doc_number] => 20240153964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => TRANSISTOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/411390 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411390
Transistor substrate including wirings connecting between transistor and driver Jan 11, 2024 Issued
Array ( [id] => 20191240 [patent_doc_number] => 12402379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Epitaxial layer under a gate structure of a transistor [patent_app_type] => utility [patent_app_number] => 18/405957 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 2088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405957
Epitaxial layer under a gate structure of a transistor Jan 4, 2024 Issued
Array ( [id] => 19131075 [patent_doc_number] => 20240136428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 18/401833 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401833
Semiconductor device including multiple inner spacers with different etch rates and method of making Jan 1, 2024 Issued
Array ( [id] => 19842701 [patent_doc_number] => 12255101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Ion implantation of nanostructures for nano-FET [patent_app_type] => utility [patent_app_number] => 18/401780 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 73 [patent_no_of_words] => 15368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401780
Ion implantation of nanostructures for nano-FET Jan 1, 2024 Issued
Array ( [id] => 19132823 [patent_doc_number] => 20240138176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/402294 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402294
Display device having stack of plurality of light emitting layers, wavelength conversion pattern, and reflective layer Jan 1, 2024 Issued
Array ( [id] => 19132823 [patent_doc_number] => 20240138176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/402294 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402294
Display device having stack of plurality of light emitting layers, wavelength conversion pattern, and reflective layer Jan 1, 2024 Issued
Array ( [id] => 19500425 [patent_doc_number] => 20240339443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/401694 [patent_app_country] => US [patent_app_date] => 2024-01-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401694 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401694
Package structure having multiple redistribution layers and manufacturing method thereof Dec 31, 2023 Issued
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