Search

Zachary W. Wilkes

Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
1061
Issued Applications
667
Pending Applications
96
Abandoned Applications
322

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8900638 [patent_doc_number] => 20130168141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'SUBSTRATE WITH THROUGH-ELECTRODE AND METHOD FOR PRODUCING SAME' [patent_app_type] => utility [patent_app_number] => 13/820758 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11392 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13820758 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/820758
SUBSTRATE WITH THROUGH-ELECTRODE AND METHOD FOR PRODUCING SAME Jan 23, 2012 Abandoned
Array ( [id] => 8198556 [patent_doc_number] => 20120122289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/356812 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5957 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20120122289.pdf [firstpage_image] =>[orig_patent_app_number] => 13356812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/356812
Semiconductor device manufacturing method Jan 23, 2012 Issued
Array ( [id] => 8185549 [patent_doc_number] => 20120115329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'DEPOSITING TUNGSTEN INTO HIGH ASPECT RATIO FEATURES' [patent_app_type] => utility [patent_app_number] => 13/351970 [patent_app_country] => US [patent_app_date] => 2012-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13306 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20120115329.pdf [firstpage_image] =>[orig_patent_app_number] => 13351970 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/351970
Depositing tungsten into high aspect ratio features Jan 16, 2012 Issued
Array ( [id] => 9135014 [patent_doc_number] => 20130295729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD FOR MANUFACTURING REVERSE-BLOCKING SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/980048 [patent_app_country] => US [patent_app_date] => 2012-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10282 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980048
Method for manufacturing reverse-blocking semiconductor element Jan 15, 2012 Issued
Array ( [id] => 9239119 [patent_doc_number] => 08603910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Method of processing a contact pad' [patent_app_type] => utility [patent_app_number] => 13/349682 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 13979 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13349682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349682
Method of processing a contact pad Jan 12, 2012 Issued
Array ( [id] => 8185473 [patent_doc_number] => 20120115299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/348415 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3520 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20120115299.pdf [firstpage_image] =>[orig_patent_app_number] => 13348415 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348415
BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR Jan 10, 2012 Abandoned
Array ( [id] => 8172693 [patent_doc_number] => 20120108041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Patterning of Nanostructures' [patent_app_type] => utility [patent_app_number] => 13/347662 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20120108041.pdf [firstpage_image] =>[orig_patent_app_number] => 13347662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347662
Patterning of nanostructures Jan 9, 2012 Issued
Array ( [id] => 9552916 [patent_doc_number] => 08759969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'Integrated circuit dice with edge finishing' [patent_app_type] => utility [patent_app_number] => 13/346076 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13346076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/346076
Integrated circuit dice with edge finishing Jan 8, 2012 Issued
Array ( [id] => 9575182 [patent_doc_number] => 08765595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Thick on-chip high-performance wiring structures' [patent_app_type] => utility [patent_app_number] => 13/345120 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7086 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13345120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345120
Thick on-chip high-performance wiring structures Jan 5, 2012 Issued
Array ( [id] => 8159484 [patent_doc_number] => 20120100726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Methods of Forming Silicon Oxides and Methods of Forming Interlevel Dielectrics' [patent_app_type] => utility [patent_app_number] => 13/338484 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3227 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20120100726.pdf [firstpage_image] =>[orig_patent_app_number] => 13338484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/338484
Methods of forming silicon oxides and methods of forming interlevel dielectrics Dec 27, 2011 Issued
Array ( [id] => 8154547 [patent_doc_number] => 20120097943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/338262 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4704 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20120097943.pdf [firstpage_image] =>[orig_patent_app_number] => 13338262 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/338262
Thin film transistor Dec 27, 2011 Issued
Array ( [id] => 9344885 [patent_doc_number] => 08664033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Absorber layer for a thin film photovoltaic device with a double-graded band gap' [patent_app_type] => utility [patent_app_number] => 13/331793 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5481 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331793 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331793
Absorber layer for a thin film photovoltaic device with a double-graded band gap Dec 19, 2011 Issued
Array ( [id] => 10165471 [patent_doc_number] => 09196704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Selective laser annealing process for buried regions in a MOS device' [patent_app_type] => utility [patent_app_number] => 13/976831 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6161 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976831 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976831
Selective laser annealing process for buried regions in a MOS device Dec 18, 2011 Issued
Array ( [id] => 8866117 [patent_doc_number] => 20130149820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/323763 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2274 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323763 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/323763
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 11, 2011 Abandoned
Array ( [id] => 8398332 [patent_doc_number] => 08268714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Method for fabricating solar cell using inductively coupled plasma chemical vapor deposition' [patent_app_type] => utility [patent_app_number] => 13/311891 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7629 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311891
Method for fabricating solar cell using inductively coupled plasma chemical vapor deposition Dec 5, 2011 Issued
Array ( [id] => 8055143 [patent_doc_number] => 20120077306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Method for Fabricating Solar Cell Using Inductively Coupled Plasma Chemical Vapor Deposition' [patent_app_type] => utility [patent_app_number] => 13/312020 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7628 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20120077306.pdf [firstpage_image] =>[orig_patent_app_number] => 13312020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/312020
Method for fabricating solar cell using inductively coupled plasma chemical vapor deposition Dec 5, 2011 Issued
Array ( [id] => 9756864 [patent_doc_number] => 20140287565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/354894 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3767 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14354894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/354894
METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Dec 1, 2011 Abandoned
Array ( [id] => 8221361 [patent_doc_number] => 20120135570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'LIFTING-OFF METHOD AND METHOD FOR MANUFACTURING TFT ARRAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/306086 [patent_app_country] => US [patent_app_date] => 2011-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4643 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13306086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/306086
Lifting-off method and method for manufacturing TFT array substrate Nov 28, 2011 Issued
Array ( [id] => 8042457 [patent_doc_number] => 20120070956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'Method for Manufacturing Memory Element' [patent_app_type] => utility [patent_app_number] => 13/304629 [patent_app_country] => US [patent_app_date] => 2011-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 21486 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20120070956.pdf [firstpage_image] =>[orig_patent_app_number] => 13304629 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304629
Method for manufacturing memory element Nov 25, 2011 Issued
Array ( [id] => 8825905 [patent_doc_number] => 20130126950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Semiconductor Device and Method of Formation' [patent_app_type] => utility [patent_app_number] => 13/304235 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304235
Semiconductor device and method of formation Nov 22, 2011 Issued
Menu