
Zachary W. Wilkes
Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )
| Most Active Art Unit | 2872 |
| Art Unit(s) | 2873, 2872 |
| Total Applications | 1061 |
| Issued Applications | 667 |
| Pending Applications | 96 |
| Abandoned Applications | 322 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18848812
[patent_doc_number] => 20230411216
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => GATE-ALL-AROUND SEMICONDUCTOR DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/362163
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10219
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362163
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362163 | Gate-all-around semiconductor device and method | Jul 30, 2023 | Issued |
Array
(
[id] => 18959130
[patent_doc_number] => 20240047457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => Power Semiconductor Device, Method of Producing a Power Semiconductor Device and Method of Operating a Power Semiconductor Device
[patent_app_type] => utility
[patent_app_number] => 18/361260
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9263
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361260
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361260 | Power semiconductor device, method of producing a power semiconductor device and method of operating a power semiconductor device | Jul 27, 2023 | Issued |
Array
(
[id] => 18812593
[patent_doc_number] => 20230386930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/361501
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10735
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361501
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361501 | Method for manufacturing semiconductor device | Jul 27, 2023 | Issued |
Array
(
[id] => 19842700
[patent_doc_number] => 12255100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Inner filler layer for multi-patterned metal gate for nanostructure transistor
[patent_app_type] => utility
[patent_app_number] => 18/361717
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 47
[patent_no_of_words] => 11195
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361717
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361717 | Inner filler layer for multi-patterned metal gate for nanostructure transistor | Jul 27, 2023 | Issued |
Array
(
[id] => 18812587
[patent_doc_number] => 20230386924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions
[patent_app_type] => utility
[patent_app_number] => 18/361354
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7916
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361354
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361354 | FinFETs with epitaxy regions having mixed wavy and non-wavy portions | Jul 27, 2023 | Issued |
Array
(
[id] => 19487286
[patent_doc_number] => 12107011
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Method for fabricating a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/360332
[patent_app_country] => US
[patent_app_date] => 2023-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 30
[patent_no_of_words] => 7149
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360332
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/360332 | Method for fabricating a semiconductor device | Jul 26, 2023 | Issued |
Array
(
[id] => 19858234
[patent_doc_number] => 12261085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Semiconductor device with reduced loading effect
[patent_app_type] => utility
[patent_app_number] => 18/359051
[patent_app_country] => US
[patent_app_date] => 2023-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7395
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359051
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/359051 | Semiconductor device with reduced loading effect | Jul 25, 2023 | Issued |
Array
(
[id] => 19751667
[patent_doc_number] => 20250040232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => SELF-ALIGNED GATE ISOLATION FOR MULTI-DIRECTIONAL GATE LAYOUTS IN QUANTUM AND SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/226189
[patent_app_country] => US
[patent_app_date] => 2023-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226189
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/226189 | Self-aligned gate isolation for multi-directional gate layouts in quantum and semiconductor devices | Jul 24, 2023 | Issued |
Array
(
[id] => 18774394
[patent_doc_number] => 20230369225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => GRAPHENE-ASSISTED LOW-RESISTANCE INTERCONNECT STRUCTURES AND METHODS OF FORMATION THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/357286
[patent_app_country] => US
[patent_app_date] => 2023-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7968
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357286
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/357286 | Graphene-assisted low-resistance interconnect structures and methods of formation thereof | Jul 23, 2023 | Issued |
Array
(
[id] => 18906267
[patent_doc_number] => 20240021752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/352200
[patent_app_country] => US
[patent_app_date] => 2023-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352200
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/352200 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING DEVICE | Jul 12, 2023 | Issued |
Array
(
[id] => 19712771
[patent_doc_number] => 20250022913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => TRENCH ISOLATION FOR BACKSIDE CONTACT FORMATION
[patent_app_type] => utility
[patent_app_number] => 18/351523
[patent_app_country] => US
[patent_app_date] => 2023-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5975
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351523
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/351523 | Trench isolation for backside contact formation | Jul 12, 2023 | Issued |
Array
(
[id] => 18757565
[patent_doc_number] => 20230361028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/221787
[patent_app_country] => US
[patent_app_date] => 2023-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9526
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221787
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/221787 | Semiconductor device including back side power supply circuit | Jul 12, 2023 | Issued |
Array
(
[id] => 19634568
[patent_doc_number] => 20240413017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/220839
[patent_app_country] => US
[patent_app_date] => 2023-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3076
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220839
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/220839 | Semiconductor device having hump in a medium-voltage region and method for fabricating the same | Jul 11, 2023 | Issued |
Array
(
[id] => 20443186
[patent_doc_number] => 12514032
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Spherical light-emitting chip and manufacturing method thereof, and display device
[patent_app_type] => utility
[patent_app_number] => 18/219820
[patent_app_country] => US
[patent_app_date] => 2023-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 14
[patent_no_of_words] => 6526
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219820
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/219820 | Spherical light-emitting chip and manufacturing method thereof, and display device | Jul 9, 2023 | Issued |
Array
(
[id] => 19200584
[patent_doc_number] => 11997848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-28
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 18/347562
[patent_app_country] => US
[patent_app_date] => 2023-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 9640
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347562
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/347562 | Memory device | Jul 5, 2023 | Issued |
Array
(
[id] => 19688183
[patent_doc_number] => 20250006728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => SELF-CLAMPING RESISTOR AND CIRCUIT FOR TRANSISTOR LINEAR REGION CURRENT MATCHING
[patent_app_type] => utility
[patent_app_number] => 18/345470
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345470
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/345470 | SELF-CLAMPING RESISTOR AND CIRCUIT FOR TRANSISTOR LINEAR REGION CURRENT MATCHING | Jun 29, 2023 | Pending |
Array
(
[id] => 19688283
[patent_doc_number] => 20250006828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/345973
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13594
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345973
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/345973 | Device structure having dielectric walls connected to a gate structure and method for manufacturing the same | Jun 29, 2023 | Issued |
Array
(
[id] => 19823594
[patent_doc_number] => 20250081801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => DISPLAY PANEL AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/288926
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8667
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18288926
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/288926 | DISPLAY PANEL AND ELECTRONIC DEVICE | Jun 29, 2023 | Pending |
Array
(
[id] => 20471020
[patent_doc_number] => 12527066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-13
[patent_title] => Gate isolation structures and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/344400
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 28
[patent_no_of_words] => 3277
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344400
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344400 | Gate isolation structures and methods of forming the same | Jun 28, 2023 | Issued |
Array
(
[id] => 20748283
[patent_doc_number] => 12648223
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Display panel and display device having different doped channel regions
[patent_app_type] => utility
[patent_app_number] => 18/288968
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3077
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18288968
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/288968 | Display panel and display device having different doped channel regions | Jun 28, 2023 | Issued |