Search

Zachary W. Wilkes

Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
1061
Issued Applications
667
Pending Applications
96
Abandoned Applications
322

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7580352 [patent_doc_number] => 20110294235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/112651 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20110294235.pdf [firstpage_image] =>[orig_patent_app_number] => 13112651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112651
METHOD OF FORMING A SEMICONDUCTOR DEVICE May 19, 2011 Abandoned
Array ( [id] => 9020915 [patent_doc_number] => 08530901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Film transistor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/096657 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2610 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13096657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096657
Film transistor and method for fabricating the same Apr 27, 2011 Issued
Array ( [id] => 6058944 [patent_doc_number] => 20110198734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'METHOD OF IMPROVING A SHALLOW TRENCH ISOLATION GAPFILL PROCESS' [patent_app_type] => utility [patent_app_number] => 13/095847 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5217 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20110198734.pdf [firstpage_image] =>[orig_patent_app_number] => 13095847 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/095847
METHOD OF IMPROVING A SHALLOW TRENCH ISOLATION GAPFILL PROCESS Apr 26, 2011 Abandoned
Array ( [id] => 8810908 [patent_doc_number] => 20130111953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'Hermetic Sealing of Glass Plates' [patent_app_type] => utility [patent_app_number] => 13/642553 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11985 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13642553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/642553
Hermetic sealing of glass plates Apr 26, 2011 Issued
Array ( [id] => 9582866 [patent_doc_number] => 08772868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Superjunction structures for power devices and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 13/095670 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 80 [patent_no_of_words] => 18364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13095670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/095670
Superjunction structures for power devices and methods of manufacture Apr 26, 2011 Issued
Array ( [id] => 7500715 [patent_doc_number] => 20110263089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/094211 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3221 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263089.pdf [firstpage_image] =>[orig_patent_app_number] => 13094211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/094211
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Apr 25, 2011 Abandoned
Array ( [id] => 8457994 [patent_doc_number] => 08293660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/093186 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 34 [patent_no_of_words] => 9369 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093186 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093186
Method of manufacturing semiconductor device Apr 24, 2011 Issued
Array ( [id] => 8465240 [patent_doc_number] => 20120270408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'MANUFACTURING METHOD OF GATE DIELECTRIC LAYER' [patent_app_type] => utility [patent_app_number] => 13/093838 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1284 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093838 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093838
MANUFACTURING METHOD OF GATE DIELECTRIC LAYER Apr 24, 2011 Abandoned
Array ( [id] => 8363586 [patent_doc_number] => 08252650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method for fabricating CMOS transistor' [patent_app_type] => utility [patent_app_number] => 13/092151 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2709 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092151 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092151
Method for fabricating CMOS transistor Apr 21, 2011 Issued
Array ( [id] => 7997201 [patent_doc_number] => 08080448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Semiconductor device with nested rows of contacts' [patent_app_type] => utility [patent_app_number] => 13/092170 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4634 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/080/08080448.pdf [firstpage_image] =>[orig_patent_app_number] => 13092170 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092170
Semiconductor device with nested rows of contacts Apr 21, 2011 Issued
Array ( [id] => 8462596 [patent_doc_number] => 20120267764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'BIPOLAR JUNCTION TRANSISTOR WITH LAYOUT CONTROLLED BASE AND ASSOCIATED METHODS OF MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 13/092699 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4502 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092699 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092699
Bipolar junction transistor with layout controlled base and associated methods of manufacturing Apr 21, 2011 Issued
Array ( [id] => 9153564 [patent_doc_number] => 08586470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Multilevel interconnect structures and methods of fabricating same' [patent_app_type] => utility [patent_app_number] => 13/091330 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 11205 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13091330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/091330
Multilevel interconnect structures and methods of fabricating same Apr 20, 2011 Issued
Array ( [id] => 8462590 [patent_doc_number] => 20120267759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'DECOUPLING CAPACITORS RECESSED IN SHALLOW TRENCH ISOLATION' [patent_app_type] => utility [patent_app_number] => 13/092046 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7995 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092046
Decoupling capacitors recessed in shallow trench isolation Apr 20, 2011 Issued
Array ( [id] => 7500710 [patent_doc_number] => 20110263084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/091194 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 32223 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263084.pdf [firstpage_image] =>[orig_patent_app_number] => 13091194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/091194
Method for manufacturing semiconductor device Apr 20, 2011 Issued
Array ( [id] => 8462488 [patent_doc_number] => 20120267656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/089485 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4766 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089485 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089485
Light emitting device and manufacturing method thereof Apr 18, 2011 Issued
Array ( [id] => 8462515 [patent_doc_number] => 20120267683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER' [patent_app_type] => utility [patent_app_number] => 13/089799 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089799 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089799
Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer Apr 18, 2011 Issued
Array ( [id] => 7654721 [patent_doc_number] => 20110303990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'Semiconductor Device and Method Making Same' [patent_app_type] => utility [patent_app_number] => 13/089529 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4194 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20110303990.pdf [firstpage_image] =>[orig_patent_app_number] => 13089529 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089529
Semiconductor Device and Method Making Same Apr 18, 2011 Abandoned
Array ( [id] => 7738105 [patent_doc_number] => 20120018340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'DEVICE HOUSING AND METHOD FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/087512 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1113 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20120018340.pdf [firstpage_image] =>[orig_patent_app_number] => 13087512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/087512
Device housing and method for making the same Apr 14, 2011 Issued
Array ( [id] => 9401598 [patent_doc_number] => 08691650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'MOSFET with recessed channel film and abrupt junctions' [patent_app_type] => utility [patent_app_number] => 13/086459 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 8254 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13086459 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/086459
MOSFET with recessed channel film and abrupt junctions Apr 13, 2011 Issued
Array ( [id] => 8450691 [patent_doc_number] => 20120261637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'OXIDE BASED MEMORY WITH A CONTROLLED OXYGEN VACANCY CONDUCTION PATH' [patent_app_type] => utility [patent_app_number] => 13/087050 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4132 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13087050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/087050
Oxide based memory with a controlled oxygen vacancy conduction path Apr 13, 2011 Issued
Menu