
Zachary W. Wilkes
Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )
| Most Active Art Unit | 2872 |
| Art Unit(s) | 2873, 2872 |
| Total Applications | 1061 |
| Issued Applications | 667 |
| Pending Applications | 96 |
| Abandoned Applications | 322 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8103693
[patent_doc_number] => 08153496
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-04-10
[patent_title] => 'Self-aligned process and method for fabrication of high efficiency solar cells'
[patent_app_type] => utility
[patent_app_number] => 13/041724
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 8
[patent_no_of_words] => 3301
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/153/08153496.pdf
[firstpage_image] =>[orig_patent_app_number] => 13041724
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041724 | Self-aligned process and method for fabrication of high efficiency solar cells | Mar 6, 2011 | Issued |
Array
(
[id] => 8457976
[patent_doc_number] => 08293642
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-23
[patent_title] => 'Method of manufacturing semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/041538
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3509
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13041538
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041538 | Method of manufacturing semiconductor devices | Mar 6, 2011 | Issued |
Array
(
[id] => 8642528
[patent_doc_number] => 08367511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-05
[patent_title] => 'Manufacturing method for high voltage transistor'
[patent_app_type] => utility
[patent_app_number] => 13/041752
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3327
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13041752
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041752 | Manufacturing method for high voltage transistor | Mar 6, 2011 | Issued |
Array
(
[id] => 7791124
[patent_doc_number] => 20120052680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-01
[patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/041543
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5227
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20120052680.pdf
[firstpage_image] =>[orig_patent_app_number] => 13041543
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041543 | Manufacturing method of semiconductor substrate | Mar 6, 2011 | Issued |
Array
(
[id] => 7712040
[patent_doc_number] => 08093104
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-01-10
[patent_title] => 'Multi-chip stacking method to reduce voids between stacked chips'
[patent_app_type] => utility
[patent_app_number] => 13/042136
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 5073
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/093/08093104.pdf
[firstpage_image] =>[orig_patent_app_number] => 13042136
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/042136 | Multi-chip stacking method to reduce voids between stacked chips | Mar 6, 2011 | Issued |
Array
(
[id] => 7696602
[patent_doc_number] => 20110229988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-22
[patent_title] => 'PATTERN FORMING METHOD, PROCESSING METHOD, AND PROCESSING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/041917
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7026
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20110229988.pdf
[firstpage_image] =>[orig_patent_app_number] => 13041917
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041917 | Pattern forming method, processing method, and processing apparatus | Mar 6, 2011 | Issued |
Array
(
[id] => 8446159
[patent_doc_number] => 08288210
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-16
[patent_title] => 'Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 13/041422
[patent_app_country] => US
[patent_app_date] => 2011-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 25
[patent_no_of_words] => 7426
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13041422
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041422 | Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package | Mar 5, 2011 | Issued |
Array
(
[id] => 7811266
[patent_doc_number] => 08133796
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-03-13
[patent_title] => 'Method for fabricating shallow trench isolation structures'
[patent_app_type] => utility
[patent_app_number] => 13/041431
[patent_app_country] => US
[patent_app_date] => 2011-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 5785
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/133/08133796.pdf
[firstpage_image] =>[orig_patent_app_number] => 13041431
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041431 | Method for fabricating shallow trench isolation structures | Mar 5, 2011 | Issued |
Array
(
[id] => 8469700
[patent_doc_number] => 08298875
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-10-30
[patent_title] => 'Method for fabrication of a semiconductor device and structure'
[patent_app_type] => utility
[patent_app_number] => 13/041404
[patent_app_country] => US
[patent_app_date] => 2011-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 377
[patent_figures_cnt] => 411
[patent_no_of_words] => 69485
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13041404
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/041404 | Method for fabrication of a semiconductor device and structure | Mar 5, 2011 | Issued |
Array
(
[id] => 8081873
[patent_doc_number] => 08148252
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-04-03
[patent_title] => 'Methods of forming III/V semiconductor materials, and semiconductor structures formed using such methods'
[patent_app_type] => utility
[patent_app_number] => 13/038920
[patent_app_country] => US
[patent_app_date] => 2011-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 11495
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/148/08148252.pdf
[firstpage_image] =>[orig_patent_app_number] => 13038920
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/038920 | Methods of forming III/V semiconductor materials, and semiconductor structures formed using such methods | Mar 1, 2011 | Issued |
Array
(
[id] => 5936949
[patent_doc_number] => 20110212593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-01
[patent_title] => 'CMP Process Flow for MEMS'
[patent_app_type] => utility
[patent_app_number] => 13/036201
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4432
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20110212593.pdf
[firstpage_image] =>[orig_patent_app_number] => 13036201
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036201 | CMP process flow for MEMS | Feb 27, 2011 | Issued |
Array
(
[id] => 8811980
[patent_doc_number] => 20130113025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/131745
[patent_app_country] => US
[patent_app_date] => 2011-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5897
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13131745
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/131745 | Semiconductor device structure and method for manufacturing the same | Feb 24, 2011 | Issued |
Array
(
[id] => 8370689
[patent_doc_number] => 20120220086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL)'
[patent_app_type] => utility
[patent_app_number] => 13/034902
[patent_app_country] => US
[patent_app_date] => 2011-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4449
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13034902
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/034902 | Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL) | Feb 24, 2011 | Issued |
Array
(
[id] => 8606717
[patent_doc_number] => 20130012029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'METHOD AND DEVICE FOR LAYER DEPOSITION'
[patent_app_type] => utility
[patent_app_number] => 13/579765
[patent_app_country] => US
[patent_app_date] => 2011-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 13696
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13579765
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/579765 | Method and device for layer deposition | Feb 22, 2011 | Issued |
Array
(
[id] => 8659630
[patent_doc_number] => 20130040459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'SUBSTRATE WIRING METHOD AND SEMICONDUCTOR MANUFACTURING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/583438
[patent_app_country] => US
[patent_app_date] => 2011-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5518
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13583438
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/583438 | Substrate wiring method and semiconductor manufacturing device | Feb 22, 2011 | Issued |
Array
(
[id] => 8814698
[patent_doc_number] => 20130115743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/063882
[patent_app_country] => US
[patent_app_date] => 2011-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3747
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13063882
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/063882 | Semiconductor device and method for forming the same | Feb 15, 2011 | Issued |
Array
(
[id] => 8560142
[patent_doc_number] => 08334205
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-18
[patent_title] => 'Method for removing polymer after etching gate stack structure of high-K gate dielectric/metal gate'
[patent_app_type] => utility
[patent_app_number] => 13/130514
[patent_app_country] => US
[patent_app_date] => 2011-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1146
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13130514
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/130514 | Method for removing polymer after etching gate stack structure of high-K gate dielectric/metal gate | Feb 14, 2011 | Issued |
Array
(
[id] => 6161960
[patent_doc_number] => 20110159690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'DEPOSITING TUNGSTEN INTO HIGH ASPECT RATIO FEATURES'
[patent_app_type] => utility
[patent_app_number] => 13/016656
[patent_app_country] => US
[patent_app_date] => 2011-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13269
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20110159690.pdf
[firstpage_image] =>[orig_patent_app_number] => 13016656
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/016656 | Depositing tungsten into high aspect ratio features | Jan 27, 2011 | Issued |
Array
(
[id] => 8642575
[patent_doc_number] => 08367559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-05
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/013554
[patent_app_country] => US
[patent_app_date] => 2011-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 52
[patent_no_of_words] => 7027
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013554
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013554 | Method of manufacturing a semiconductor device | Jan 24, 2011 | Issued |
Array
(
[id] => 9227412
[patent_doc_number] => 08633080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-21
[patent_title] => 'Methods of making multi-state non-volatile memory cells'
[patent_app_type] => utility
[patent_app_number] => 13/004985
[patent_app_country] => US
[patent_app_date] => 2011-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 25
[patent_no_of_words] => 4720
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13004985
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/004985 | Methods of making multi-state non-volatile memory cells | Jan 11, 2011 | Issued |