Search

Zachary W. Wilkes

Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
1061
Issued Applications
667
Pending Applications
96
Abandoned Applications
322

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6609394 [patent_doc_number] => 20100099248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Methods of fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/588564 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20100099248.pdf [firstpage_image] =>[orig_patent_app_number] => 12588564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588564
Methods of fabricating a semiconductor device Oct 19, 2009 Issued
Array ( [id] => 7740415 [patent_doc_number] => 08105956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Methods of forming silicon oxides and methods of forming interlevel dielectrics' [patent_app_type] => utility [patent_app_number] => 12/582181 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 3227 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/105/08105956.pdf [firstpage_image] =>[orig_patent_app_number] => 12582181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582181
Methods of forming silicon oxides and methods of forming interlevel dielectrics Oct 19, 2009 Issued
Array ( [id] => 7712021 [patent_doc_number] => 08093090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-10 [patent_title] => 'Integrated circuit edge and method to fabricate the same' [patent_app_type] => utility [patent_app_number] => 12/577602 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6100 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093090.pdf [firstpage_image] =>[orig_patent_app_number] => 12577602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577602
Integrated circuit edge and method to fabricate the same Oct 11, 2009 Issued
Array ( [id] => 4571527 [patent_doc_number] => 07829448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-09 [patent_title] => 'Structure of high electron mobility transistor, a device comprising the structure and a method of producing the same' [patent_app_type] => utility [patent_app_number] => 12/574702 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2254 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/829/07829448.pdf [firstpage_image] =>[orig_patent_app_number] => 12574702 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574702
Structure of high electron mobility transistor, a device comprising the structure and a method of producing the same Oct 6, 2009 Issued
Array ( [id] => 4557517 [patent_doc_number] => 07838334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Package-on-package device, semiconductor package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/565501 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838334.pdf [firstpage_image] =>[orig_patent_app_number] => 12565501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565501
Package-on-package device, semiconductor package and method for manufacturing the same Sep 22, 2009 Issued
Array ( [id] => 4624219 [patent_doc_number] => 08003515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Device and manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/562701 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 6250 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003515.pdf [firstpage_image] =>[orig_patent_app_number] => 12562701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562701
Device and manufacturing method Sep 17, 2009 Issued
Array ( [id] => 4474436 [patent_doc_number] => 07867821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-11 [patent_title] => 'Integrated circuit package system with through semiconductor vias and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/562702 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3304 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/867/07867821.pdf [firstpage_image] =>[orig_patent_app_number] => 12562702 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562702
Integrated circuit package system with through semiconductor vias and method of manufacture thereof Sep 17, 2009 Issued
Array ( [id] => 7795742 [patent_doc_number] => 08124448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Semiconductor chip with crack deflection structure' [patent_app_type] => utility [patent_app_number] => 12/562902 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4866 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/124/08124448.pdf [firstpage_image] =>[orig_patent_app_number] => 12562902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562902
Semiconductor chip with crack deflection structure Sep 17, 2009 Issued
Array ( [id] => 7545383 [patent_doc_number] => 08053354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Reduced wafer warpage in semiconductors by stress engineering in the metallization system' [patent_app_type] => utility [patent_app_number] => 12/561701 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8313 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053354.pdf [firstpage_image] =>[orig_patent_app_number] => 12561701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561701
Reduced wafer warpage in semiconductors by stress engineering in the metallization system Sep 16, 2009 Issued
Array ( [id] => 6279871 [patent_doc_number] => 20100155716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'THIN FILM TRANSISTOR USING BORON-DOPED OXIDE SEMICONDUCTOR THIN FILM AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/560702 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155716.pdf [firstpage_image] =>[orig_patent_app_number] => 12560702 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560702
Method of fabricating a thin film transistor using boron-doped oxide semiconductor thin film Sep 15, 2009 Issued
Array ( [id] => 8398263 [patent_doc_number] => 08268643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Substrate, epitaxial layer provided substrate, method for producing substrate, and method for producing epitaxial layer provided substrate' [patent_app_type] => utility [patent_app_number] => 13/062590 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 19811 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13062590 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/062590
Substrate, epitaxial layer provided substrate, method for producing substrate, and method for producing epitaxial layer provided substrate Sep 3, 2009 Issued
Array ( [id] => 6427065 [patent_doc_number] => 20100151617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Method of growing silicon and method of manufacturing solar cell using the same' [patent_app_type] => utility [patent_app_number] => 12/461502 [patent_app_country] => US [patent_app_date] => 2009-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20100151617.pdf [firstpage_image] =>[orig_patent_app_number] => 12461502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461502
Method of growing silicon and method of manufacturing solar cell using the same Aug 12, 2009 Issued
Array ( [id] => 6632012 [patent_doc_number] => 20100035371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Method for Fabricating Light Emitting Device' [patent_app_type] => utility [patent_app_number] => 12/536069 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 29377 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20100035371.pdf [firstpage_image] =>[orig_patent_app_number] => 12536069 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/536069
Method for fabricating light emitting device Aug 4, 2009 Issued
Array ( [id] => 6105836 [patent_doc_number] => 20110186830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'Method of Making Organic Thin Film Transistors Using a Laser Induced Thermal Transfer Printing Process' [patent_app_type] => utility [patent_app_number] => 13/056906 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6353 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186830.pdf [firstpage_image] =>[orig_patent_app_number] => 13056906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/056906
Organic thin film transistors and methods of making them Aug 4, 2009 Issued
Array ( [id] => 6632097 [patent_doc_number] => 20100035379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/535713 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 25277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20100035379.pdf [firstpage_image] =>[orig_patent_app_number] => 12535713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/535713
Method for manufacturing semiconductor device Aug 4, 2009 Issued
Array ( [id] => 7774005 [patent_doc_number] => 08119527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Depositing tungsten into high aspect ratio features' [patent_app_type] => utility [patent_app_number] => 12/535464 [patent_app_country] => US [patent_app_date] => 2009-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8026 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119527.pdf [firstpage_image] =>[orig_patent_app_number] => 12535464 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/535464
Depositing tungsten into high aspect ratio features Aug 3, 2009 Issued
Array ( [id] => 4582289 [patent_doc_number] => 07851236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Film thickness prediction method, layout design method, mask pattern design method of exposure mask, and fabrication method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/534254 [patent_app_country] => US [patent_app_date] => 2009-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 14655 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851236.pdf [firstpage_image] =>[orig_patent_app_number] => 12534254 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534254
Film thickness prediction method, layout design method, mask pattern design method of exposure mask, and fabrication method of semiconductor integrated circuit Aug 2, 2009 Issued
Array ( [id] => 6193122 [patent_doc_number] => 20110024876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'CREATION OF THIN GROUP II-VI MONOCRYSTALLINE LAYERS BY ION CUTTING TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 12/533253 [patent_app_country] => US [patent_app_date] => 2009-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6398 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20110024876.pdf [firstpage_image] =>[orig_patent_app_number] => 12533253 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/533253
CREATION OF THIN GROUP II-VI MONOCRYSTALLINE LAYERS BY ION CUTTING TECHNIQUES Jul 30, 2009 Abandoned
Array ( [id] => 7515277 [patent_doc_number] => 08039349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Methods for fabricating non-planar semiconductor devices having stress memory' [patent_app_type] => utility [patent_app_number] => 12/512814 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5040 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/039/08039349.pdf [firstpage_image] =>[orig_patent_app_number] => 12512814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512814
Methods for fabricating non-planar semiconductor devices having stress memory Jul 29, 2009 Issued
Array ( [id] => 6255023 [patent_doc_number] => 20100029020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'SUBSTRATE PROCESSING CONTROL METHOD AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/511749 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6480 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20100029020.pdf [firstpage_image] =>[orig_patent_app_number] => 12511749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511749
Substrate processing control method and storage medium Jul 28, 2009 Issued
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