
Zannatul Ferdous
Examiner (ID: 5289, Phone: (571)270-0399 , Office: P/2867 )
| Most Active Art Unit | 2858 |
| Art Unit(s) | 2858, 2867 |
| Total Applications | 874 |
| Issued Applications | 704 |
| Pending Applications | 93 |
| Abandoned Applications | 98 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18712802
[patent_doc_number] => 20230335435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/338730
[patent_app_country] => US
[patent_app_date] => 2023-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15475
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338730
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/338730 | INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF | Jun 20, 2023 | Pending |
Array
(
[id] => 19662091
[patent_doc_number] => 20240429156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-26
[patent_title] => Embedding Metal-Insulator-Metal Structure In Silicon Oxide In A Copper Redistribution Layer Scheme
[patent_app_type] => utility
[patent_app_number] => 18/337963
[patent_app_country] => US
[patent_app_date] => 2023-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6600
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337963
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/337963 | Embedding Metal-Insulator-Metal Structure In Silicon Oxide In A Copper Redistribution Layer Scheme | Jun 19, 2023 | Pending |
Array
(
[id] => 20612866
[patent_doc_number] => 12588487
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Tight pitch directional selective via growth
[patent_app_type] => utility
[patent_app_number] => 18/211283
[patent_app_country] => US
[patent_app_date] => 2023-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 2117
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211283
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/211283 | Tight pitch directional selective via growth | Jun 17, 2023 | Issued |
Array
(
[id] => 20720215
[patent_doc_number] => 12635487
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-19
[patent_title] => Semiconductor backside isolation feature for merged epitaxy
[patent_app_type] => utility
[patent_app_number] => 18/336063
[patent_app_country] => US
[patent_app_date] => 2023-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 37
[patent_no_of_words] => 6158
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336063
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/336063 | Semiconductor backside isolation feature for merged epitaxy | Jun 15, 2023 | Issued |
Array
(
[id] => 19646556
[patent_doc_number] => 20240421076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => ADVANCED INTERCONNECTS WITH HYPERBOLOID PROFILE
[patent_app_type] => utility
[patent_app_number] => 18/333642
[patent_app_country] => US
[patent_app_date] => 2023-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333642
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/333642 | ADVANCED INTERCONNECTS WITH HYPERBOLOID PROFILE | Jun 12, 2023 | Pending |
Array
(
[id] => 19559907
[patent_doc_number] => 20240371699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => Semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/208896
[patent_app_country] => US
[patent_app_date] => 2023-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208896
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/208896 | Semiconductor structure and manufacturing method thereof | Jun 12, 2023 | Issued |
Array
(
[id] => 19619191
[patent_doc_number] => 20240404871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => METHODS FOR ISOLATION PROCESS CONTROL AND STRUCTURES THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/205001
[patent_app_country] => US
[patent_app_date] => 2023-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6436
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205001
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/205001 | METHODS FOR ISOLATION PROCESS CONTROL AND STRUCTURES THEREOF | Jun 1, 2023 | Pending |
Array
(
[id] => 20692153
[patent_doc_number] => 12622329
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => Interposer frame and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/321219
[patent_app_country] => US
[patent_app_date] => 2023-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 364
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321219
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/321219 | Interposer frame and method of manufacturing the same | May 21, 2023 | Issued |
Array
(
[id] => 19733785
[patent_doc_number] => 12211787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Interconnect structures and methods of fabrication thereof
[patent_app_type] => utility
[patent_app_number] => 18/309460
[patent_app_country] => US
[patent_app_date] => 2023-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 8138
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309460
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/309460 | Interconnect structures and methods of fabrication thereof | Apr 27, 2023 | Issued |
Array
(
[id] => 19935104
[patent_doc_number] => 12308312
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Interconnect structure and method for manufacturing the interconnect structure
[patent_app_type] => utility
[patent_app_number] => 18/305528
[patent_app_country] => US
[patent_app_date] => 2023-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 6335
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305528
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/305528 | Interconnect structure and method for manufacturing the interconnect structure | Apr 23, 2023 | Issued |
Array
(
[id] => 18586128
[patent_doc_number] => 20230268393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/303855
[patent_app_country] => US
[patent_app_date] => 2023-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10962
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303855
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/303855 | Semiconductor device and method | Apr 19, 2023 | Issued |
Array
(
[id] => 19935106
[patent_doc_number] => 12308314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Metal loss prevention in conductive structures
[patent_app_type] => utility
[patent_app_number] => 18/135563
[patent_app_country] => US
[patent_app_date] => 2023-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2266
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135563
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/135563 | Metal loss prevention in conductive structures | Apr 16, 2023 | Issued |
Array
(
[id] => 19515692
[patent_doc_number] => 20240347378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING A PLANARIZATION AND SEMICONDUCTOR STRUCTURE THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/133058
[patent_app_country] => US
[patent_app_date] => 2023-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8914
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133058
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/133058 | Method of manufacturing semiconductor structure including a planarization and semiconductor structure thereof | Apr 10, 2023 | Issued |
Array
(
[id] => 20496894
[patent_doc_number] => 12538788
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-27
[patent_title] => Semiconductor device with filling layer and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 18/132418
[patent_app_country] => US
[patent_app_date] => 2023-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 4563
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132418
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/132418 | Semiconductor device with filling layer and method for fabricating the same | Apr 9, 2023 | Issued |
Array
(
[id] => 18833967
[patent_doc_number] => 20230402494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/194802
[patent_app_country] => US
[patent_app_date] => 2023-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7908
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194802
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/194802 | Semiconductor device and method of manufacturing the same | Apr 2, 2023 | Issued |
Array
(
[id] => 19484206
[patent_doc_number] => 20240332248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => DIRECT HYBRID BONDING IN TOPOGRAPHIC PACKAGES
[patent_app_type] => utility
[patent_app_number] => 18/194571
[patent_app_country] => US
[patent_app_date] => 2023-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12240
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194571
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/194571 | DIRECT HYBRID BONDING IN TOPOGRAPHIC PACKAGES | Mar 30, 2023 | Pending |
Array
(
[id] => 19116370
[patent_doc_number] => 20240128120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/192679
[patent_app_country] => US
[patent_app_date] => 2023-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5280
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/192679 | Package structure and method for fabricating the same | Mar 29, 2023 | Issued |
Array
(
[id] => 19467961
[patent_doc_number] => 20240321631
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => BACK-END-OF-LINE (BEOL) INTERCONNECTS WITH DIFFERENT AIRGAP HEIGHTS AND METAL TRACE CORNER PROTECTION STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/190024
[patent_app_country] => US
[patent_app_date] => 2023-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7646
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190024
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/190024 | BACK-END-OF-LINE (BEOL) INTERCONNECTS WITH DIFFERENT AIRGAP HEIGHTS AND METAL TRACE CORNER PROTECTION STRUCTURES | Mar 23, 2023 | Pending |
Array
(
[id] => 20484035
[patent_doc_number] => 12532514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-20
[patent_title] => Semiconductor structure with isolation region including combination of deep and shallow trench isolation structures and method
[patent_app_type] => utility
[patent_app_number] => 18/182926
[patent_app_country] => US
[patent_app_date] => 2023-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 34
[patent_no_of_words] => 2364
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182926
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/182926 | Semiconductor structure with isolation region including combination of deep and shallow trench isolation structures and method | Mar 12, 2023 | Issued |
Array
(
[id] => 18473190
[patent_doc_number] => 20230207478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => Method of Forming RDLS and Structure Formed Thereof
[patent_app_type] => utility
[patent_app_number] => 18/179083
[patent_app_country] => US
[patent_app_date] => 2023-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9108
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179083
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/179083 | Method of forming RDLs and structure formed thereof | Mar 5, 2023 | Issued |