Zheng B. Song

Array ( [id] => 17389092 [patent_doc_number] => 20220036944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/187526 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18480995 [patent_doc_number] => 11694746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/184980 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 16045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18528537 [patent_doc_number] => 11715535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/181660 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 12569 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18357940 [patent_doc_number] => 11646347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Semiconductor device having transistors in which source/drain regions are shared [patent_app_type] => utility [patent_app_number] => 17/179198 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18347432 [patent_doc_number] => 20230135542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => CONSTANT VOLTAGE GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/798619 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17798619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304248 [patent_doc_number] => 11626160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Dynamic sense node voltage to compensate for variances when sensing threshold voltages of memory cells [patent_app_type] => utility [patent_app_number] => 17/166612 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 22286 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18548045 [patent_doc_number] => 11721403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Method of programming and verifying memory device and related memory device [patent_app_type] => utility [patent_app_number] => 17/164795 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5127 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17779857 [patent_doc_number] => 20220246207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => ERROR AVOIDANCE BASED ON VOLTAGE DISTRIBUTION PARAMETERS [patent_app_type] => utility [patent_app_number] => 17/164636 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17818365 [patent_doc_number] => 11423986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor memory device and method of operating the semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/160015 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 14772 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17277685 [patent_doc_number] => 20210383883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/154576 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17731427 [patent_doc_number] => 11387831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Dynamic calibration of frequency and power storage interface [patent_app_type] => utility [patent_app_number] => 17/152486 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17485689 [patent_doc_number] => 20220093193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => ARCHITECTURE AND METHOD FOR NAND MEMORY PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/149080 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17573940 [patent_doc_number] => 11322214 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Gaussian modeling for soft-read threshold estimation in non-volatile memory devices [patent_app_type] => utility [patent_app_number] => 17/147770 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17723171 [patent_doc_number] => 20220215893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => MEMORY APPARATUS AND MEMORY TESTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/142208 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17716390 [patent_doc_number] => 11380388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Memory arrays with vertical thin film transistors coupled between digit lines [patent_app_type] => utility [patent_app_number] => 17/140540 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5374 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708257 [patent_doc_number] => 20220208265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY DEVICE WITH ON-CHIP SACRIFICIAL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/139059 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781417 [patent_doc_number] => 20210118496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD FOR OPERATING A NON-VOLATILE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/134471 [patent_app_country] => US [patent_app_date] => 2020-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16752520 [patent_doc_number] => 20210104532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => MEMORY DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/125303 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18463162 [patent_doc_number] => 11687452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Dynamic program-verify voltage adjustment for intra-block storage charge loss uniformity [patent_app_type] => utility [patent_app_number] => 17/123244 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18796719 [patent_doc_number] => 11830545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Data programming techniques to store multiple bits of data per memory cell with high reliability [patent_app_type] => utility [patent_app_number] => 17/124380 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9803 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124380 [rel_patent_id] =>[rel_patent_doc_number] =>)