
Zheng B. Song
Examiner (ID: 3906, Phone: (571)272-9402 , Office: P/2875 )
| Most Active Art Unit | 2875 |
| Art Unit(s) | 2875, 2885 |
| Total Applications | 872 |
| Issued Applications | 597 |
| Pending Applications | 74 |
| Abandoned Applications | 220 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15299533
[patent_doc_number] => 20190392902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-26
[patent_title] => NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/553891
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553891
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/553891 | Nonvolatile memory device and program method of the same | Aug 27, 2019 | Issued |
Array
(
[id] => 15271551
[patent_doc_number] => 20190384510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => STORAGE DEVICE AND DATA STORING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/551754
[patent_app_country] => US
[patent_app_date] => 2019-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551754
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/551754 | Storage device and data storing method thereof | Aug 26, 2019 | Issued |
Array
(
[id] => 15672469
[patent_doc_number] => 10600473
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => Apparatuses and methods to perform logical operations using sensing circuitry
[patent_app_type] => utility
[patent_app_number] => 16/549554
[patent_app_country] => US
[patent_app_date] => 2019-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 10639
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549554
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/549554 | Apparatuses and methods to perform logical operations using sensing circuitry | Aug 22, 2019 | Issued |
Array
(
[id] => 15217407
[patent_doc_number] => 20190371390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-05
[patent_title] => APPARATUSES AND METHODS FOR DETECTING A ROW HAMMER ATTACK WITH A BANDPASS FILTER
[patent_app_type] => utility
[patent_app_number] => 16/545489
[patent_app_country] => US
[patent_app_date] => 2019-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6205
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545489
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/545489 | Apparatuses and methods for detecting a row hammer attack with a bandpass filter | Aug 19, 2019 | Issued |
Array
(
[id] => 16896067
[patent_doc_number] => 11037628
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Methods of operating nonvolatile memory devices, methods of operating storage device and storage devices
[patent_app_type] => utility
[patent_app_number] => 16/543532
[patent_app_country] => US
[patent_app_date] => 2019-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 25
[patent_no_of_words] => 9849
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543532
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/543532 | Methods of operating nonvolatile memory devices, methods of operating storage device and storage devices | Aug 16, 2019 | Issued |
Array
(
[id] => 16616991
[patent_doc_number] => 20210035644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => MEMORY APPARATUS AND DATA ACCESS METHOD FOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/529553
[patent_app_country] => US
[patent_app_date] => 2019-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529553
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/529553 | MEMORY APPARATUS AND DATA ACCESS METHOD FOR MEMORY | Jul 31, 2019 | Abandoned |
Array
(
[id] => 15122965
[patent_doc_number] => 20190348116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-14
[patent_title] => CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC
[patent_app_type] => utility
[patent_app_number] => 16/525432
[patent_app_country] => US
[patent_app_date] => 2019-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11550
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525432
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/525432 | CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC | Jul 28, 2019 | Abandoned |
Array
(
[id] => 17224485
[patent_doc_number] => 11176995
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-16
[patent_title] => Cross-point array of polymer junctions with individually-programmed conductances
[patent_app_type] => utility
[patent_app_number] => 16/515486
[patent_app_country] => US
[patent_app_date] => 2019-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5887
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515486
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/515486 | Cross-point array of polymer junctions with individually-programmed conductances | Jul 17, 2019 | Issued |
Array
(
[id] => 16586344
[patent_doc_number] => 20210020746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-21
[patent_title] => SEMICONDUCTOR DEVICE HAVING TRANSISTORS IN WHICH SOURCE/DRAIN REGIONS ARE SHARED
[patent_app_type] => utility
[patent_app_number] => 16/514828
[patent_app_country] => US
[patent_app_date] => 2019-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514828
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/514828 | Semiconductor device having transistors in which source/drain regions are shared | Jul 16, 2019 | Issued |
Array
(
[id] => 15042553
[patent_doc_number] => 20190332281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => WEAR LEVELING
[patent_app_type] => utility
[patent_app_number] => 16/510236
[patent_app_country] => US
[patent_app_date] => 2019-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5928
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510236
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/510236 | Wear leveling | Jul 11, 2019 | Issued |
Array
(
[id] => 16077969
[patent_doc_number] => 20200192971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => NAND BLOCK ARCHITECTURE FOR IN-MEMORY MULTIPLY-AND-ACCUMULATE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 16/508189
[patent_app_country] => US
[patent_app_date] => 2019-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8013
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508189
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/508189 | NAND block architecture for in-memory multiply-and-accumulate operations | Jul 9, 2019 | Issued |
Array
(
[id] => 15045193
[patent_doc_number] => 20190333601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => POST-PACKAGING REPAIR OF REDUNDANT ROWS
[patent_app_type] => utility
[patent_app_number] => 16/505271
[patent_app_country] => US
[patent_app_date] => 2019-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5820
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505271
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/505271 | Post-packaging repair of redundant rows | Jul 7, 2019 | Issued |
Array
(
[id] => 17121908
[patent_doc_number] => 11133048
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-28
[patent_title] => Charge-mirror based sensing for ferroelectric memory
[patent_app_type] => utility
[patent_app_number] => 16/504876
[patent_app_country] => US
[patent_app_date] => 2019-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14263
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504876
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/504876 | Charge-mirror based sensing for ferroelectric memory | Jul 7, 2019 | Issued |
Array
(
[id] => 16818556
[patent_doc_number] => 11003382
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-11
[patent_title] => Apparatus for outputting internal state of memory apparatus and memory system using the apparatus
[patent_app_type] => utility
[patent_app_number] => 16/503116
[patent_app_country] => US
[patent_app_date] => 2019-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 26
[patent_no_of_words] => 11440
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503116
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/503116 | Apparatus for outputting internal state of memory apparatus and memory system using the apparatus | Jul 2, 2019 | Issued |
Array
(
[id] => 16536294
[patent_doc_number] => 10878907
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-29
[patent_title] => Sub-block size reduction for 3D non-volatile memory
[patent_app_type] => utility
[patent_app_number] => 16/432304
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 26
[patent_no_of_words] => 13880
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432304
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/432304 | Sub-block size reduction for 3D non-volatile memory | Jun 4, 2019 | Issued |
Array
(
[id] => 15597151
[patent_doc_number] => 20200075110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => NONVOLATILE MEMORY AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/429588
[patent_app_country] => US
[patent_app_date] => 2019-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28815
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429588
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/429588 | Nonvolatile memory and memory system | Jun 2, 2019 | Issued |
Array
(
[id] => 14842601
[patent_doc_number] => 20190279701
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => DUAL MODE MEMORY SYSTEM AND METHOD OF WORKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/424485
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2888
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424485
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424485 | Dual mode memory system and method of working the same | May 28, 2019 | Issued |
Array
(
[id] => 16495500
[patent_doc_number] => 10861547
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-08
[patent_title] => Multi-step reset technique to enlarge memory window
[patent_app_type] => utility
[patent_app_number] => 16/417705
[patent_app_country] => US
[patent_app_date] => 2019-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7629
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417705
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/417705 | Multi-step reset technique to enlarge memory window | May 20, 2019 | Issued |
Array
(
[id] => 16495523
[patent_doc_number] => 10861570
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Memory device and an operating method of a memory device
[patent_app_type] => utility
[patent_app_number] => 16/418509
[patent_app_country] => US
[patent_app_date] => 2019-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 8658
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418509
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/418509 | Memory device and an operating method of a memory device | May 20, 2019 | Issued |
Array
(
[id] => 16417592
[patent_doc_number] => 10825492
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-03
[patent_title] => Methods and apparatuses for command shifter reduction
[patent_app_type] => utility
[patent_app_number] => 16/416425
[patent_app_country] => US
[patent_app_date] => 2019-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5957
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416425
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/416425 | Methods and apparatuses for command shifter reduction | May 19, 2019 | Issued |