Search

Zheng Wei

Examiner (ID: 5332, Phone: (571)270-1059 , Office: P/2192 )

Most Active Art Unit
2192
Art Unit(s)
2192
Total Applications
566
Issued Applications
433
Pending Applications
2
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17645396 [patent_doc_number] => 20220173135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines [patent_app_type] => utility [patent_app_number] => 17/107242 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107242
Array of capacitors, an array of memory cells, method used in forming an array of memory cells, methods used in forming an array of capacitors, and methods used in forming a plurality of horizontally-spaced conductive lines Nov 29, 2020 Issued
Array ( [id] => 18355109 [patent_doc_number] => 11643499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Liquid molding compound for protecting five edges of semiconductor chip and preparation method thereof [patent_app_type] => utility [patent_app_number] => 17/911431 [patent_app_country] => US [patent_app_date] => 2020-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2188 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17911431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/911431
Liquid molding compound for protecting five edges of semiconductor chip and preparation method thereof Nov 26, 2020 Issued
Array ( [id] => 17439116 [patent_doc_number] => 11264457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => Isolation trenches augmented with a trap-rich layer [patent_app_type] => utility [patent_app_number] => 16/953897 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953897
Isolation trenches augmented with a trap-rich layer Nov 19, 2020 Issued
Array ( [id] => 17893191 [patent_doc_number] => 11456171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Deep trench integration processes and devices [patent_app_type] => utility [patent_app_number] => 16/953577 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5041 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953577
Deep trench integration processes and devices Nov 19, 2020 Issued
Array ( [id] => 17590675 [patent_doc_number] => 11328952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Interconnect structure and method [patent_app_type] => utility [patent_app_number] => 17/099263 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 10534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099263
Interconnect structure and method Nov 15, 2020 Issued
Array ( [id] => 18016118 [patent_doc_number] => 11508421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Electronic devices comprising air gaps adjacent to bitlines and related methods and systems [patent_app_type] => utility [patent_app_number] => 17/097494 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8200 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097494
Electronic devices comprising air gaps adjacent to bitlines and related methods and systems Nov 12, 2020 Issued
Array ( [id] => 17456204 [patent_doc_number] => 11271071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Integrated system with power management integrated circuit having on-chip thin film inductors [patent_app_type] => utility [patent_app_number] => 17/096824 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 11345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096824 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096824
Integrated system with power management integrated circuit having on-chip thin film inductors Nov 11, 2020 Issued
Array ( [id] => 17166283 [patent_doc_number] => 11152395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-19 [patent_title] => Monolithic multi-FETs [patent_app_type] => utility [patent_app_number] => 17/096688 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 14536 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096688
Monolithic multi-FETs Nov 11, 2020 Issued
Array ( [id] => 16850649 [patent_doc_number] => 20210151394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/095277 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095277
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 10, 2020 Abandoned
Array ( [id] => 17599578 [patent_doc_number] => 20220149152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => CO-INTEGRATED HIGH VOLTAGE (HV) AND MEDIUM VOLTAGE (MV) FIELD EFFECT TRANSISTORS WITH DEFECT PREVENTION STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/091382 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/091382
Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors with defect prevention structures Nov 5, 2020 Issued
Array ( [id] => 17353351 [patent_doc_number] => 11227998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Organic light-emitting display apparatus and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/090681 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 10480 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090681
Organic light-emitting display apparatus and method of manufacturing the same Nov 4, 2020 Issued
Array ( [id] => 17456145 [patent_doc_number] => 11271012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => Method for improving size of contact holes of FDSOI device [patent_app_type] => utility [patent_app_number] => 17/088514 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4079 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 508 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088514 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088514
Method for improving size of contact holes of FDSOI device Nov 2, 2020 Issued
Array ( [id] => 17493426 [patent_doc_number] => 11282739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Methods for removing an oxide film from a SOI structure and methods for preparing a SOI structure [patent_app_type] => utility [patent_app_number] => 17/085422 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 7233 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085422
Methods for removing an oxide film from a SOI structure and methods for preparing a SOI structure Oct 29, 2020 Issued
Array ( [id] => 17439053 [patent_doc_number] => 11264394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors [patent_app_type] => utility [patent_app_number] => 17/083208 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7882 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083208
Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors Oct 27, 2020 Issued
Array ( [id] => 17566668 [patent_doc_number] => 20220130817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => POWER DISTRIBUTION NETWORK [patent_app_type] => utility [patent_app_number] => 17/081807 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081807
Power distribution network Oct 26, 2020 Issued
Array ( [id] => 16624979 [patent_doc_number] => 20210043632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => BURIED WORD LINE OF A DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/079537 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079537 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079537
Buried word line of a dynamic random access memory and method for fabricating the same Oct 25, 2020 Issued
Array ( [id] => 16617300 [patent_doc_number] => 20210035953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => DEVICES EMPLOYING THERMAL AND MECHANICAL ENHANCED LAYERS AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/073888 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073888
Devices employing thermal and mechanical enhanced layers and methods of forming same Oct 18, 2020 Issued
Array ( [id] => 17925962 [patent_doc_number] => 11469225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation [patent_app_type] => utility [patent_app_number] => 17/072649 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072649
Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation Oct 15, 2020 Issued
Array ( [id] => 17381222 [patent_doc_number] => 11239255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Integrated circuit with active region jogs [patent_app_type] => utility [patent_app_number] => 17/071845 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071845
Integrated circuit with active region jogs Oct 14, 2020 Issued
Array ( [id] => 17262955 [patent_doc_number] => 20210375940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND METHODS OF FORMING [patent_app_type] => utility [patent_app_number] => 17/070619 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070619
Three-dimensional memory device and methods of forming Oct 13, 2020 Issued
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