Search

Zhihan Zhou

Examiner (ID: 9641, Phone: (571)270-7284 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
1130
Issued Applications
848
Pending Applications
107
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18874401 [patent_doc_number] => 11862222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Refresh circuit and memory [patent_app_type] => utility [patent_app_number] => 17/456635 [patent_app_country] => US [patent_app_date] => 2021-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5376 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456635
Refresh circuit and memory Nov 26, 2021 Issued
Array ( [id] => 19080030 [patent_doc_number] => 11949415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Logic operation circuit for computation in memory [patent_app_type] => utility [patent_app_number] => 17/534805 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3916 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534805
Logic operation circuit for computation in memory Nov 23, 2021 Issued
Array ( [id] => 19093701 [patent_doc_number] => 11955165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Memories and memory components with interconnected and redundant data interfaces [patent_app_type] => utility [patent_app_number] => 17/532745 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 10041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532745
Memories and memory components with interconnected and redundant data interfaces Nov 21, 2021 Issued
Array ( [id] => 18379452 [patent_doc_number] => 20230154541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SOFT ERASE PROCESS DURING PROGRAMMING OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/530196 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530196
Soft erase process during programming of non-volatile memory Nov 17, 2021 Issued
Array ( [id] => 19459946 [patent_doc_number] => 12100448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Storage device and data writing method [patent_app_type] => utility [patent_app_number] => 17/530128 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10567 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530128
Storage device and data writing method Nov 17, 2021 Issued
Array ( [id] => 19030292 [patent_doc_number] => 11929663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Power management integrated circuit with charge pump [patent_app_type] => utility [patent_app_number] => 17/527661 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5904 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527661
Power management integrated circuit with charge pump Nov 15, 2021 Issued
Array ( [id] => 19031345 [patent_doc_number] => 11930723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-12 [patent_title] => Systems and methods for dynamically reconfigurable artificial synapses and neurons with tunable activation functions [patent_app_type] => utility [patent_app_number] => 17/522006 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522006 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522006
Systems and methods for dynamically reconfigurable artificial synapses and neurons with tunable activation functions Nov 8, 2021 Issued
Array ( [id] => 18623573 [patent_doc_number] => 11756626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Memory die resource management [patent_app_type] => utility [patent_app_number] => 17/520398 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520398
Memory die resource management Nov 4, 2021 Issued
Array ( [id] => 18339020 [patent_doc_number] => 20230130969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => Providing Data from Portions of a Memory to Processors in Memory (PIMs) in an Electronic Device [patent_app_type] => utility [patent_app_number] => 17/512662 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512662
Providing data from portions of a memory to processors in memory (PIMs) in an electronic device Oct 26, 2021 Issued
Array ( [id] => 17551321 [patent_doc_number] => 20220122663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => POLARITY-WRITTEN CELL ARCHITECTURES FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/511484 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511484
Polarity-written cell architectures for a memory device Oct 25, 2021 Issued
Array ( [id] => 19314202 [patent_doc_number] => 12040026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution [patent_app_type] => utility [patent_app_number] => 17/506587 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 20318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506587
Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution Oct 19, 2021 Issued
Array ( [id] => 19399493 [patent_doc_number] => 12073878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Processing element and electronic device including processing element [patent_app_type] => utility [patent_app_number] => 17/505956 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 9423 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505956
Processing element and electronic device including processing element Oct 19, 2021 Issued
Array ( [id] => 19314192 [patent_doc_number] => 12040016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Crossbar circuits for performing convolution operations [patent_app_type] => utility [patent_app_number] => 17/504478 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13127 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504478
Crossbar circuits for performing convolution operations Oct 17, 2021 Issued
Array ( [id] => 19108468 [patent_doc_number] => 11961581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Assemblies comprising memory cells and select gates; and methods of forming assemblies [patent_app_type] => utility [patent_app_number] => 17/499218 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499218
Assemblies comprising memory cells and select gates; and methods of forming assemblies Oct 11, 2021 Issued
Array ( [id] => 17582631 [patent_doc_number] => 20220139486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE, OPERATING METHOD OF STORAGE DEVICE, AND OPERATING METHOD OF ELECTRONIC DEVICE INCLUDING NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/488989 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488989
Storage device including nonvolatile memory device, operating method of storage device, and operating method of electronic device including nonvolatile memory device Sep 28, 2021 Issued
Array ( [id] => 18265509 [patent_doc_number] => 20230086751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => BLOCK LIST MANAGEMENT FOR WORDLINE START VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/483279 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483279
Block list management for wordline start voltage Sep 22, 2021 Issued
Array ( [id] => 17615101 [patent_doc_number] => 20220157381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => MEMORY DEVICE, A MEMORY SYSTEM, AND A METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/483088 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483088
Method of operating a memory device by performing a program operation using a coarse verification voltage and a fine verification voltage and a memory device and a memory system employing the same Sep 22, 2021 Issued
Array ( [id] => 18137087 [patent_doc_number] => 11562775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/463526 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3158 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463526
Semiconductor device Aug 30, 2021 Issued
Array ( [id] => 17402631 [patent_doc_number] => 20220044722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => TECHNIQUES FOR ACCESSING AN ARRAY OF MEMORY CELLS TO REDUCE PARASITIC COUPLING [patent_app_type] => utility [patent_app_number] => 17/411721 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411721 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411721
Techniques for accessing an array of memory cells to reduce parasitic coupling Aug 24, 2021 Issued
Array ( [id] => 19596782 [patent_doc_number] => 12154635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Memory programming techniques to reduce power consumption [patent_app_type] => utility [patent_app_number] => 17/410265 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 12067 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410265
Memory programming techniques to reduce power consumption Aug 23, 2021 Issued
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