Zhihan Zhou

Array ( [id] => 17246812 [patent_doc_number] => 20210366557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => MEMORY APPARATUS AND ASSOCIATED CONTROL METHOD FOR REDUCING ERASE DISTURB OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/178313 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17825856 [patent_doc_number] => 11430811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => 3D NAND memory device with select gate cut [patent_app_type] => utility [patent_app_number] => 17/154054 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 14042 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16795858 [patent_doc_number] => 20210125675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SCAN OPTIMIZATION FROM STACKING MULTIPLE RELIABILITY SPECIFICATIONS [patent_app_type] => utility [patent_app_number] => 17/141964 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17402653 [patent_doc_number] => 20220044744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => BALANCED THREE-LEVEL READ DISTURB MANAGEMENT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/132490 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16850353 [patent_doc_number] => 20210151098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => UTILIZING NAND BUFFER FOR DRAM-LESS MULTILEVEL CELL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/133459 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16920127 [patent_doc_number] => 20210193219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => Temperature Tracked Dynamic Keeper Implementation to Enable Read Operations [patent_app_type] => utility [patent_app_number] => 17/133103 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16752270 [patent_doc_number] => 20210104282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => MULTI-BIT MEMORY SYSTEM WITH ADAPTIVE READ VOLTAGE CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/126649 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17676378 [patent_doc_number] => 20220189545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => MANAGING READ LEVEL VOLTAGE OFFSETS FOR LOW THRESHOLD VOLTAGE OFFSET BIN PLACEMENTS [patent_app_type] => utility [patent_app_number] => 17/124144 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17573926 [patent_doc_number] => 11322200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Single-rail memory circuit with row-specific voltage supply lines and boost circuits [patent_app_type] => utility [patent_app_number] => 17/120325 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18280118 [patent_doc_number] => 20230095590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => BIAS CURRENT GENERATION CIRCUIT AND FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/799459 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660469 [patent_doc_number] => 20220180934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => READ WINDOW BUDGET OPTIMIZATION FOR THREE DIMENSIONAL CROSSPOINT MEMORY [patent_app_type] => utility [patent_app_number] => 17/114980 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17818370 [patent_doc_number] => 11423991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Method and apparatus for data erase in memory devices [patent_app_type] => utility [patent_app_number] => 17/113582 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17438772 [patent_doc_number] => 11264112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Trim setting determination for a memory device [patent_app_type] => utility [patent_app_number] => 17/111755 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16715342 [patent_doc_number] => 20210082489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => TIME TRACKING CIRCUIT FOR FRAM [patent_app_type] => utility [patent_app_number] => 17/108041 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17231994 [patent_doc_number] => 20210358551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM [patent_app_type] => utility [patent_app_number] => 17/082956 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -53 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17878361 [patent_doc_number] => 11450382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Memory cell state in a valley between adjacent data states [patent_app_type] => utility [patent_app_number] => 17/074156 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7504 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16585828 [patent_doc_number] => 20210020230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => MEMORY DEVICES AND METHODS OF CONTROLLING AN AUTO-REFRESH OPERATION OF THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/064111 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18415821 [patent_doc_number] => 11670366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Non-destructive mode cache programming in NAND flash memory devices [patent_app_type] => utility [patent_app_number] => 17/062867 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8413 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17447820 [patent_doc_number] => 20220068325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY CELL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/034540 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16730912 [patent_doc_number] => 20210098060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => NON-VOLATILE MULTI-LEVEL CELL MEMORY USING A FERROELECTRIC SUPERLATTICE AND RELATED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/032847 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032847 [rel_patent_id] =>[rel_patent_doc_number] =>)