Search

Zhihan Zhou

Examiner (ID: 9641, Phone: (571)270-7284 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
1130
Issued Applications
848
Pending Applications
107
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17438757 [patent_doc_number] => 11264097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Voltage generation circuit and semiconductor circuit including the voltage generation circuit [patent_app_type] => utility [patent_app_number] => 16/906784 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3120 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906784
Voltage generation circuit and semiconductor circuit including the voltage generation circuit Jun 18, 2020 Issued
Array ( [id] => 16402377 [patent_doc_number] => 20200343235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH LOGIC SIGNAL ROUTING THROUGH A MEMORY DIE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/900486 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900486
Three-dimensional memory device with logic signal routing through a memory die and methods of making the same Jun 11, 2020 Issued
Array ( [id] => 19356713 [patent_doc_number] => 12057168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Neighbor aware multi-bias programming in scaled BICS [patent_app_type] => utility [patent_app_number] => 16/899860 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 15620 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899860
Neighbor aware multi-bias programming in scaled BICS Jun 11, 2020 Issued
Array ( [id] => 16904497 [patent_doc_number] => 20210183413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM HAVING INPUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/894498 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16894498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/894498
Input circuit capable of stabilizing power voltage and memory device including the same Jun 4, 2020 Issued
Array ( [id] => 17288919 [patent_doc_number] => 11205476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Read data processing circuits and methods associated with computational memory cells [patent_app_type] => utility [patent_app_number] => 16/886537 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7786 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886537
Read data processing circuits and methods associated with computational memory cells May 27, 2020 Issued
Array ( [id] => 17262378 [patent_doc_number] => 20210375363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 16/884137 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884137
Memory device comprising source line coupled to multiple memory cells and method of operation May 26, 2020 Issued
Array ( [id] => 16781406 [patent_doc_number] => 20210118485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/881351 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881351
Memory device having program current adjustible based on detected holding voltage May 21, 2020 Issued
Array ( [id] => 17231971 [patent_doc_number] => 20210358528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => Physically Unclonable Function Circuit Having Lower Gate-to-Source/Drain Breakdown Voltage [patent_app_type] => utility [patent_app_number] => 16/876092 [patent_app_country] => US [patent_app_date] => 2020-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876092
Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage May 16, 2020 Issued
Array ( [id] => 18967228 [patent_doc_number] => 11901006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Shiftable memory and method of operating a shiftable memory [patent_app_type] => utility [patent_app_number] => 17/611364 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 10285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/611364
Shiftable memory and method of operating a shiftable memory May 13, 2020 Issued
Array ( [id] => 16858103 [patent_doc_number] => 20210158848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/872072 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/872072
Semiconductor memory device configured to output data based on a warm-up cycle and operating method thereof May 10, 2020 Issued
Array ( [id] => 16723513 [patent_doc_number] => 20210090660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/866149 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866149 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866149
Memory device performing program operation and method of operating the same May 3, 2020 Issued
Array ( [id] => 16752279 [patent_doc_number] => 20210104291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => MEMORY, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/855373 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/855373
Memory, memory system having the same and operating method thereof Apr 21, 2020 Issued
Array ( [id] => 17878776 [patent_doc_number] => 11450802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Thermally sensitive ionic redox transistor [patent_app_type] => utility [patent_app_number] => 16/854151 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854151
Thermally sensitive ionic redox transistor Apr 20, 2020 Issued
Array ( [id] => 17825850 [patent_doc_number] => 11430805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Semiconductor memory device including three-dimensional memory cell arrays [patent_app_type] => utility [patent_app_number] => 16/852990 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4658 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/852990
Semiconductor memory device including three-dimensional memory cell arrays Apr 19, 2020 Issued
Array ( [id] => 16210510 [patent_doc_number] => 20200243500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR CHIP CONTAINING MEMORY DIE BONDED TO BOTH SIDES OF A SUPPORT DIE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/848137 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848137
Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same Apr 13, 2020 Issued
Array ( [id] => 17158782 [patent_doc_number] => 20210319833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING [patent_app_type] => utility [patent_app_number] => 16/845249 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845249
APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING Apr 9, 2020 Abandoned
Array ( [id] => 16193902 [patent_doc_number] => 20200234751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/838585 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838585
Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays Apr 1, 2020 Issued
Array ( [id] => 17130069 [patent_doc_number] => 20210304838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => INTERCONNECTED COMMAND/ADDRESS RESOURCES [patent_app_type] => utility [patent_app_number] => 16/836646 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836646
Interconnected command/address resources Mar 30, 2020 Issued
Array ( [id] => 16180159 [patent_doc_number] => 20200227128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => MEMORY DEVICES CONFIGURED TO TEST DATA PATH INTEGRITY [patent_app_type] => utility [patent_app_number] => 16/827751 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827751
Memory devices configured to test data path integrity Mar 23, 2020 Issued
Array ( [id] => 16347747 [patent_doc_number] => 20200312398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => Ferroelectric Domain Regulated Optical Readout Mode Memory And Preparing Method Thereof [patent_app_type] => utility [patent_app_number] => 16/823410 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823410
Ferroelectric domain regulated optical readout mode memory and preparing method thereof Mar 18, 2020 Issued
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