Search

Zhihan Zhou

Examiner (ID: 9641, Phone: (571)270-7284 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
1130
Issued Applications
848
Pending Applications
107
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18652814 [patent_doc_number] => 20230298654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR DIRECT REFRESH MANAGEMENT SAMPLING PROTECTION [patent_app_type] => utility [patent_app_number] => 17/695568 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695568
Apparatuses, systems, and methods for direct refresh management sampling protection Mar 14, 2022 Issued
Array ( [id] => 18210233 [patent_doc_number] => 20230056494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/695529 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695529
Semiconductor memory device Mar 14, 2022 Issued
Array ( [id] => 18394564 [patent_doc_number] => 20230162785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => NON-VOLATILE MEMORY BASED COMPUTE-IN-MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/695578 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695578
Non-volatile memory based compute-in-memory cell Mar 14, 2022 Issued
Array ( [id] => 18228150 [patent_doc_number] => 20230067144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/692447 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692447
Memory controller that transmits hammer addresses with different command protocols and memory system including the same Mar 10, 2022 Issued
Array ( [id] => 18237898 [patent_doc_number] => 20230070208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/683153 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683153
Ganged single level cell verify in a memory device Feb 27, 2022 Issued
Array ( [id] => 18240076 [patent_doc_number] => 20230072387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MULTI-BIT WRITING AND VERIFICATION IN SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/682255 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682255
Multi-bit writing and verification in semiconductor memory device Feb 27, 2022 Issued
Array ( [id] => 18766757 [patent_doc_number] => 11817164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Trim setting determination for a memory device [patent_app_type] => utility [patent_app_number] => 17/680502 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5423 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680502
Trim setting determination for a memory device Feb 24, 2022 Issued
Array ( [id] => 17645479 [patent_doc_number] => 20220173218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND DEFECT DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/674385 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674385
SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND DEFECT DETECTION METHOD Feb 16, 2022 Abandoned
Array ( [id] => 18555040 [patent_doc_number] => 20230253056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => PRE-POSITION DUMMY WORD LINE TO FACILITATE WRITE ERASE CAPABILITY OF MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/665267 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665267 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665267
Pre-position dummy word line to facilitate write erase capability of memory apparatus Feb 3, 2022 Issued
Array ( [id] => 19093692 [patent_doc_number] => 11955156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays [patent_app_type] => utility [patent_app_number] => 17/589603 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5858 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589603
Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays Jan 30, 2022 Issued
Array ( [id] => 17706745 [patent_doc_number] => 20220206751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => TERNARY IN-MEMORY ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/588311 [patent_app_country] => US [patent_app_date] => 2022-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588311
Ternary in-memory accelerator Jan 29, 2022 Issued
Array ( [id] => 18211949 [patent_doc_number] => 20230058213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MEMORY DEVICE, METHOD OF MANUFACTURING MEMORY DEVICE AND METHOD OF OPERATING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/573338 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573338
Memory device, method of manufacturing memory device and method of operating memory device Jan 10, 2022 Issued
Array ( [id] => 18486953 [patent_doc_number] => 20230214299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => READ CALIBRATION BY SECTOR OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/566921 [patent_app_country] => US [patent_app_date] => 2021-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566921
Read calibration by sector of memory Dec 30, 2021 Issued
Array ( [id] => 18061427 [patent_doc_number] => 20220392513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/565743 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565743
Memory device including predecoder and operating method thereof Dec 29, 2021 Issued
Array ( [id] => 17551318 [patent_doc_number] => 20220122660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => CONFIGURATION AND METHOD OF OPERATION OF A ONE-TRANSISTOR TWO-RESISTORS (1T2R) RESISTIVE MEMORY (RERAM) CELL AND AN ARRAY THEREOF [patent_app_type] => utility [patent_app_number] => 17/565777 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565777
CONFIGURATION AND METHOD OF OPERATION OF A ONE-TRANSISTOR TWO-RESISTORS (1T2R) RESISTIVE MEMORY (RERAM) CELL AND AN ARRAY THEREOF Dec 29, 2021 Pending
Array ( [id] => 18039747 [patent_doc_number] => 20220383964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => FLASH MEMORY, METHOD OF ERASING THE SAME AND ELECTRONIC SYSTEM [patent_app_type] => utility [patent_app_number] => 17/566253 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566253
Method of erasing flash memory and electronic system Dec 29, 2021 Issued
Array ( [id] => 18918973 [patent_doc_number] => 11881261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => CAMs for low latency complex distribution sampling [patent_app_type] => utility [patent_app_number] => 17/555260 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555260
CAMs for low latency complex distribution sampling Dec 16, 2021 Issued
Array ( [id] => 18974944 [patent_doc_number] => 20240055036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => ELECTRIC CIRCUIT ASSEMBLY COMPRISING A FERROELECTRIC FIELD EFFECT TRANSISTOR, AND MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/267797 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18267797 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/267797
ELECTRIC CIRCUIT ASSEMBLY COMPRISING A FERROELECTRIC FIELD EFFECT TRANSISTOR, AND MEMORY CELL Dec 13, 2021 Pending
Array ( [id] => 18158077 [patent_doc_number] => 20230024668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/550234 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550234
Memory device for generating pump clock and operating method of the memory device Dec 13, 2021 Issued
Array ( [id] => 17660467 [patent_doc_number] => 20220180932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => OPTIMIZATION OF REFERENCE VOLTAGES IN A NON-VOLATILE MEMORY (NVM) [patent_app_type] => utility [patent_app_number] => 17/541973 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541973
Optimization of reference voltages in a non-volatile memory (NVM) Dec 2, 2021 Issued
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