
Zhipeng Wang
Examiner (ID: 17407, Phone: (571)272-5437 , Office: P/2115 )
| Most Active Art Unit | 2115 |
| Art Unit(s) | 2115 |
| Total Applications | 564 |
| Issued Applications | 425 |
| Pending Applications | 67 |
| Abandoned Applications | 101 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3480481
[patent_doc_number] => 05405794
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-11
[patent_title] => 'Method of producing VDMOS device of increased power density'
[patent_app_type] => 1
[patent_app_number] => 8/259769
[patent_app_country] => US
[patent_app_date] => 1994-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2386
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 595
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/405/05405794.pdf
[firstpage_image] =>[orig_patent_app_number] => 259769
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/259769 | Method of producing VDMOS device of increased power density | Jun 13, 1994 | Issued |
Array
(
[id] => 3454000
[patent_doc_number] => 05378655
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Method of manufacturing a semiconductor device comprising an insulated gate field effect device'
[patent_app_type] => 1
[patent_app_number] => 8/221293
[patent_app_country] => US
[patent_app_date] => 1994-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4811
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/378/05378655.pdf
[firstpage_image] =>[orig_patent_app_number] => 221293
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/221293 | Method of manufacturing a semiconductor device comprising an insulated gate field effect device | Mar 30, 1994 | Issued |
Array
(
[id] => 3459207
[patent_doc_number] => 05382535
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-17
[patent_title] => 'Method of fabricating performance lateral double-diffused MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/213887
[patent_app_country] => US
[patent_app_date] => 1994-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2653
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/382/05382535.pdf
[firstpage_image] =>[orig_patent_app_number] => 213887
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/213887 | Method of fabricating performance lateral double-diffused MOS transistor | Mar 15, 1994 | Issued |
Array
(
[id] => 3444422
[patent_doc_number] => 05397721
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Method for fabricating vertical thin film transistor'
[patent_app_type] => 1
[patent_app_number] => 8/186795
[patent_app_country] => US
[patent_app_date] => 1994-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 2403
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/397/05397721.pdf
[firstpage_image] =>[orig_patent_app_number] => 186795
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/186795 | Method for fabricating vertical thin film transistor | Jan 24, 1994 | Issued |
Array
(
[id] => 3038423
[patent_doc_number] => 05376559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-27
[patent_title] => 'Method of manufacturing a lateral field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/172731
[patent_app_country] => US
[patent_app_date] => 1993-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2578
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/376/05376559.pdf
[firstpage_image] =>[orig_patent_app_number] => 172731
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/172731 | Method of manufacturing a lateral field effect transistor | Dec 26, 1993 | Issued |
Array
(
[id] => 3070954
[patent_doc_number] => 05360749
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-01
[patent_title] => 'Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface'
[patent_app_type] => 1
[patent_app_number] => 8/166305
[patent_app_country] => US
[patent_app_date] => 1993-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4167
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/360/05360749.pdf
[firstpage_image] =>[orig_patent_app_number] => 166305
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/166305 | Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface | Dec 9, 1993 | Issued |
Array
(
[id] => 3450182
[patent_doc_number] => 05385852
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Method for manufacturing vertical MOS transistors'
[patent_app_type] => 1
[patent_app_number] => 8/163523
[patent_app_country] => US
[patent_app_date] => 1993-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3015
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/385/05385852.pdf
[firstpage_image] =>[orig_patent_app_number] => 163523
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/163523 | Method for manufacturing vertical MOS transistors | Dec 8, 1993 | Issued |
Array
(
[id] => 3052176
[patent_doc_number] => 05344789
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'Method of manufacturing vertical DMOS transistor with high off-breakdown-voltage and low on-resistance'
[patent_app_type] => 1
[patent_app_number] => 8/155801
[patent_app_country] => US
[patent_app_date] => 1993-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 5946
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/344/05344789.pdf
[firstpage_image] =>[orig_patent_app_number] => 155801
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/155801 | Method of manufacturing vertical DMOS transistor with high off-breakdown-voltage and low on-resistance | Nov 22, 1993 | Issued |
Array
(
[id] => 3029175
[patent_doc_number] => 05342795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-30
[patent_title] => 'Method of fabricating power VFET gate-refill'
[patent_app_type] => 1
[patent_app_number] => 8/153121
[patent_app_country] => US
[patent_app_date] => 1993-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 20
[patent_no_of_words] => 3360
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/342/05342795.pdf
[firstpage_image] =>[orig_patent_app_number] => 153121
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/153121 | Method of fabricating power VFET gate-refill | Nov 14, 1993 | Issued |
Array
(
[id] => 3459853
[patent_doc_number] => 05391501
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Method for manufacturing integrated circuits with a step for replacing defective circuit elements'
[patent_app_type] => 1
[patent_app_number] => 8/147569
[patent_app_country] => US
[patent_app_date] => 1993-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 34
[patent_no_of_words] => 7497
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 275
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/391/05391501.pdf
[firstpage_image] =>[orig_patent_app_number] => 147569
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/147569 | Method for manufacturing integrated circuits with a step for replacing defective circuit elements | Nov 4, 1993 | Issued |
| 08/135866 | METHOD OF FABRICATING RANDOM ACCESS MEMORY DEVICE | Oct 12, 1993 | Abandoned |
Array
(
[id] => 3415222
[patent_doc_number] => 05393676
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-28
[patent_title] => 'Method of fabricating semiconductor gate electrode with fluorine migration barrier'
[patent_app_type] => 1
[patent_app_number] => 8/125421
[patent_app_country] => US
[patent_app_date] => 1993-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3745
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/393/05393676.pdf
[firstpage_image] =>[orig_patent_app_number] => 125421
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/125421 | Method of fabricating semiconductor gate electrode with fluorine migration barrier | Sep 21, 1993 | Issued |
Array
(
[id] => 3045514
[patent_doc_number] => 05304500
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-19
[patent_title] => 'Method of making electro-optical detector array'
[patent_app_type] => 1
[patent_app_number] => 8/089461
[patent_app_country] => US
[patent_app_date] => 1993-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 5513
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/304/05304500.pdf
[firstpage_image] =>[orig_patent_app_number] => 089461
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/089461 | Method of making electro-optical detector array | Jul 11, 1993 | Issued |
Array
(
[id] => 3056971
[patent_doc_number] => 05338703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-16
[patent_title] => 'Method for producing a recessed gate field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/086895
[patent_app_country] => US
[patent_app_date] => 1993-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 44
[patent_no_of_words] => 4119
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/338/05338703.pdf
[firstpage_image] =>[orig_patent_app_number] => 086895
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086895 | Method for producing a recessed gate field effect transistor | Jul 6, 1993 | Issued |
Array
(
[id] => 3093207
[patent_doc_number] => 05369045
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Method for forming a self-aligned lateral DMOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/086773
[patent_app_country] => US
[patent_app_date] => 1993-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2370
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/369/05369045.pdf
[firstpage_image] =>[orig_patent_app_number] => 086773
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086773 | Method for forming a self-aligned lateral DMOS transistor | Jun 30, 1993 | Issued |
Array
(
[id] => 3107104
[patent_doc_number] => 05407850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'SOI transistor threshold optimization by use of gate oxide having positive charge'
[patent_app_type] => 1
[patent_app_number] => 8/085321
[patent_app_country] => US
[patent_app_date] => 1993-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1422
[patent_no_of_claims] => 1
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/407/05407850.pdf
[firstpage_image] =>[orig_patent_app_number] => 085321
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/085321 | SOI transistor threshold optimization by use of gate oxide having positive charge | Jun 28, 1993 | Issued |
Array
(
[id] => 3478131
[patent_doc_number] => 05399508
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-21
[patent_title] => 'Method for self-aligned punchthrough implant using an etch-back gate'
[patent_app_type] => 1
[patent_app_number] => 8/081993
[patent_app_country] => US
[patent_app_date] => 1993-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2827
[patent_no_of_claims] => 39
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/399/05399508.pdf
[firstpage_image] =>[orig_patent_app_number] => 081993
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/081993 | Method for self-aligned punchthrough implant using an etch-back gate | Jun 22, 1993 | Issued |
Array
(
[id] => 3450167
[patent_doc_number] => 05385851
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Method of manufacturing HEMT device using novolak-based positive-type resist'
[patent_app_type] => 1
[patent_app_number] => 8/075383
[patent_app_country] => US
[patent_app_date] => 1993-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3732
[patent_no_of_claims] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/385/05385851.pdf
[firstpage_image] =>[orig_patent_app_number] => 075383
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/075383 | Method of manufacturing HEMT device using novolak-based positive-type resist | Jun 13, 1993 | Issued |
Array
(
[id] => 3038971
[patent_doc_number] => 05376589
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-27
[patent_title] => 'Method of fabricating similar indexed dissociated chips'
[patent_app_type] => 1
[patent_app_number] => 8/070371
[patent_app_country] => US
[patent_app_date] => 1993-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/376/05376589.pdf
[firstpage_image] =>[orig_patent_app_number] => 070371
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/070371 | Method of fabricating similar indexed dissociated chips | Jun 2, 1993 | Issued |
Array
(
[id] => 3093507
[patent_doc_number] => 05369060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Method for dicing composite wafers'
[patent_app_type] => 1
[patent_app_number] => 8/070141
[patent_app_country] => US
[patent_app_date] => 1993-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/369/05369060.pdf
[firstpage_image] =>[orig_patent_app_number] => 070141
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/070141 | Method for dicing composite wafers | May 31, 1993 | Issued |