Search

Zhitong Chen

Examiner (ID: 12313, Phone: (571)270-1936 , Office: P/2649 )

Most Active Art Unit
2649
Art Unit(s)
2647, 2616, 2649
Total Applications
691
Issued Applications
469
Pending Applications
93
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14049285 [patent_doc_number] => 20190080749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/190557 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16190557 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/190557
Semiconductor device Nov 13, 2018 Issued
Array ( [id] => 14163529 [patent_doc_number] => 20190108867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => CHARGE MIRROR-BASED SENSING FOR FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/189425 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189425
Charge mirror-based sensing for ferroelectric memory Nov 12, 2018 Issued
Array ( [id] => 16896061 [patent_doc_number] => 11037622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor device and dynamic logic circuit [patent_app_type] => utility [patent_app_number] => 16/759013 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 14886 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16759013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/759013
Semiconductor device and dynamic logic circuit Nov 11, 2018 Issued
Array ( [id] => 16372168 [patent_doc_number] => 10803934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Mixed cross point memory [patent_app_type] => utility [patent_app_number] => 16/185154 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185154
Mixed cross point memory Nov 8, 2018 Issued
Array ( [id] => 16308461 [patent_doc_number] => 10777266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Mixed cross point memory [patent_app_type] => utility [patent_app_number] => 16/185146 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185146
Mixed cross point memory Nov 8, 2018 Issued
Array ( [id] => 14616567 [patent_doc_number] => 10360987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Managing refresh for flash memory [patent_app_type] => utility [patent_app_number] => 16/175745 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5051 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175745
Managing refresh for flash memory Oct 29, 2018 Issued
Array ( [id] => 15351085 [patent_doc_number] => 20200013434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => NON-VOLATILE MEMORY WITH CAPACITORS USING METAL UNDER PADS [patent_app_type] => utility [patent_app_number] => 16/168168 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168168
Non-volatile memory with capacitors using metal under pads Oct 22, 2018 Issued
Array ( [id] => 14721939 [patent_doc_number] => 20190252033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => TECHNIQUES FOR PROVIDING SIGNAL CALIBRATION DATA [patent_app_type] => utility [patent_app_number] => 16/168809 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168809
Techniques for providing signal calibration data Oct 22, 2018 Issued
Array ( [id] => 13933673 [patent_doc_number] => 20190050352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => MEMORY SYSTEM INCLUDING ON-DIE TERMINATION AND METHOD OF CONTROLLING ON-DIE TERMINATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/165139 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165139
Memory system including on-die termination and method of controlling on-die termination thereof Oct 18, 2018 Issued
Array ( [id] => 15791751 [patent_doc_number] => 10629607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-21 [patent_title] => Semiconductor CMOS non-volatile memory device [patent_app_type] => utility [patent_app_number] => 16/158099 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1833 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158099 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/158099
Semiconductor CMOS non-volatile memory device Oct 10, 2018 Issued
Array ( [id] => 15775189 [patent_doc_number] => 20200118612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MONOTONIC VARIABLE DELAY LINE [patent_app_type] => utility [patent_app_number] => 16/156341 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16156341 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/156341
Monotonic variable delay line Oct 9, 2018 Issued
Array ( [id] => 16746201 [patent_doc_number] => 10971200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor circuit and operating method for the same [patent_app_type] => utility [patent_app_number] => 16/154831 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3460 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154831
Semiconductor circuit and operating method for the same Oct 8, 2018 Issued
Array ( [id] => 15640753 [patent_doc_number] => 10593378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/152549 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5722 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152549
Memory device Oct 4, 2018 Issued
Array ( [id] => 16172620 [patent_doc_number] => 10714196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Methods for determining data states of memory cells [patent_app_type] => utility [patent_app_number] => 16/152897 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 14898 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152897
Methods for determining data states of memory cells Oct 4, 2018 Issued
Array ( [id] => 16132037 [patent_doc_number] => 10699785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Computing memory architecture [patent_app_type] => utility [patent_app_number] => 16/144771 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144771 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/144771
Computing memory architecture Sep 26, 2018 Issued
Array ( [id] => 16308470 [patent_doc_number] => 10777275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Reset refresh techniques for self-selecting memory [patent_app_type] => utility [patent_app_number] => 16/143033 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143033
Reset refresh techniques for self-selecting memory Sep 25, 2018 Issued
Array ( [id] => 15077175 [patent_doc_number] => 10468082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-05 [patent_title] => MRAM sense amplifier having a pre-amplifier with improved output offset cancellation [patent_app_type] => utility [patent_app_number] => 16/140417 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140417
MRAM sense amplifier having a pre-amplifier with improved output offset cancellation Sep 23, 2018 Issued
Array ( [id] => 17745435 [patent_doc_number] => 11393514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Turbo mode SRAM for high performance [patent_app_type] => utility [patent_app_number] => 16/139779 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139779 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139779
Turbo mode SRAM for high performance Sep 23, 2018 Issued
Array ( [id] => 15984235 [patent_doc_number] => 10672452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Temperature informed memory refresh [patent_app_type] => utility [patent_app_number] => 16/138115 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10220 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138115
Temperature informed memory refresh Sep 20, 2018 Issued
Array ( [id] => 15657263 [patent_doc_number] => 20200091162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => ONE TRANSISTOR AND ONE FERROELECTRIC CAPACITOR MEMORY CELLS IN DIAGONAL ARRANGEMENTS [patent_app_type] => utility [patent_app_number] => 16/132281 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132281
One transistor and one ferroelectric capacitor memory cells in diagonal arrangements Sep 13, 2018 Issued
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