Search

Zhuo H. Li

Examiner (ID: 16500, Phone: (571)272-4183 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2185, 2189, 2186, 2133
Total Applications
817
Issued Applications
685
Pending Applications
71
Abandoned Applications
83

Applications

Application numberTitle of the applicationFiling DateStatus
19/112735 FPGA-BASED MASK MATCHING METHOD AND SYSTEM Mar 17, 2025 Pending
Array ( [id] => 19848706 [patent_doc_number] => 20250094057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SYSTEMS, METHODS, AND MEDIA FOR CONTROLLING BACKGROUND WEAR LEVELING IN SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 18/962759 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18962759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/962759
SYSTEMS, METHODS, AND MEDIA FOR CONTROLLING BACKGROUND WEAR LEVELING IN SOLID-STATE DRIVES Nov 26, 2024 Pending
Array ( [id] => 19771892 [patent_doc_number] => 20250053318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => DYNAMIC MANAGEMENT OF A MEMORY FIREWALL [patent_app_type] => utility [patent_app_number] => 18/932199 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932199
DYNAMIC MANAGEMENT OF A MEMORY FIREWALL Oct 29, 2024 Pending
Array ( [id] => 19771892 [patent_doc_number] => 20250053318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => DYNAMIC MANAGEMENT OF A MEMORY FIREWALL [patent_app_type] => utility [patent_app_number] => 18/932199 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932199
DYNAMIC MANAGEMENT OF A MEMORY FIREWALL Oct 29, 2024 Pending
Array ( [id] => 19725736 [patent_doc_number] => 20250028487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MEMORY DEVICES INCLUDING IDLE TIME PREDICTION [patent_app_type] => utility [patent_app_number] => 18/906236 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906236
MEMORY DEVICES INCLUDING IDLE TIME PREDICTION Oct 3, 2024 Pending
Array ( [id] => 19725736 [patent_doc_number] => 20250028487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MEMORY DEVICES INCLUDING IDLE TIME PREDICTION [patent_app_type] => utility [patent_app_number] => 18/906236 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906236
MEMORY DEVICES INCLUDING IDLE TIME PREDICTION Oct 3, 2024 Pending
Array ( [id] => 19864423 [patent_doc_number] => 20250103209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/891579 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891579
MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER Sep 19, 2024 Pending
Array ( [id] => 19864423 [patent_doc_number] => 20250103209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/891579 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891579
MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER Sep 19, 2024 Pending
Array ( [id] => 19864423 [patent_doc_number] => 20250103209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/891579 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891579
MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER Sep 19, 2024 Pending
Array ( [id] => 19644823 [patent_doc_number] => 20240419343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 18/820442 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820442
REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE Aug 29, 2024 Pending
Array ( [id] => 19633030 [patent_doc_number] => 20240411479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => REDUCED DATA REPRESENTATION MEMORY CONTROLLER AND RELATED CHIPLET SETS [patent_app_type] => utility [patent_app_number] => 18/809778 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18809778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/809778
REDUCED DATA REPRESENTATION MEMORY CONTROLLER AND RELATED CHIPLET SETS Aug 19, 2024 Pending
Array ( [id] => 20195316 [patent_doc_number] => 20250272026 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-08-28 [patent_title] => MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/771865 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771865
MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES Jul 11, 2024 Pending
Array ( [id] => 20195316 [patent_doc_number] => 20250272026 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-08-28 [patent_title] => MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/771865 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771865
MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES Jul 11, 2024 Pending
Array ( [id] => 20195316 [patent_doc_number] => 20250272026 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-08-28 [patent_title] => MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/771865 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771865
MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES Jul 11, 2024 Pending
Array ( [id] => 20195316 [patent_doc_number] => 20250272026 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-08-28 [patent_title] => MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/771865 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771865
MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES Jul 11, 2024 Pending
Array ( [id] => 19544885 [patent_doc_number] => 20240361921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE AND PROGRAM SPEED CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/767529 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767529
MEMORY DEVICE AND PROGRAM SPEED CONTROL METHOD THEREOF Jul 8, 2024 Pending
Array ( [id] => 20139187 [patent_doc_number] => 20250246231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => DUAL TRACKING FOR FLY BIT LINE STATIC RANDOM ACCESS MEMORY (SRAM) ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/756659 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756659
DUAL TRACKING FOR FLY BIT LINE STATIC RANDOM ACCESS MEMORY (SRAM) ARCHITECTURE Jun 26, 2024 Pending
Array ( [id] => 20139187 [patent_doc_number] => 20250246231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => DUAL TRACKING FOR FLY BIT LINE STATIC RANDOM ACCESS MEMORY (SRAM) ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/756659 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756659
DUAL TRACKING FOR FLY BIT LINE STATIC RANDOM ACCESS MEMORY (SRAM) ARCHITECTURE Jun 26, 2024 Pending
Array ( [id] => 20145527 [patent_doc_number] => 12379869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Adjustable function-in-memory computation system [patent_app_type] => utility [patent_app_number] => 18/744351 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744351
Adjustable function-in-memory computation system Jun 13, 2024 Issued
Array ( [id] => 20145527 [patent_doc_number] => 12379869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Adjustable function-in-memory computation system [patent_app_type] => utility [patent_app_number] => 18/744351 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744351
Adjustable function-in-memory computation system Jun 13, 2024 Issued
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