Search

Zhuo H. Li

Examiner (ID: 15574, Phone: (571)272-4183 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2185, 2133, 2186, 2189
Total Applications
846
Issued Applications
701
Pending Applications
71
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20139183 [patent_doc_number] => 20250246227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => MEMORY CONTROLLER PERFORMING TRAINING AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/887624 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887624 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887624
MEMORY CONTROLLER PERFORMING TRAINING AND OPERATION METHOD THEREOF Sep 16, 2024 Pending
Array ( [id] => 19644823 [patent_doc_number] => 20240419343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 18/820442 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820442
REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE Aug 29, 2024 Pending
Array ( [id] => 19850401 [patent_doc_number] => 20250095752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/821670 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821670
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM Aug 29, 2024 Pending
Array ( [id] => 19633030 [patent_doc_number] => 20240411479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => REDUCED DATA REPRESENTATION MEMORY CONTROLLER AND RELATED CHIPLET SETS [patent_app_type] => utility [patent_app_number] => 18/809778 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18809778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/809778
REDUCED DATA REPRESENTATION MEMORY CONTROLLER AND RELATED CHIPLET SETS Aug 19, 2024 Pending
Array ( [id] => 20702932 [patent_doc_number] => 12625643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Sampling-based read enabling window generation method [patent_app_type] => utility [patent_app_number] => 18/805782 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805782
Sampling-based read enabling window generation method Aug 14, 2024 Issued
Array ( [id] => 20291072 [patent_doc_number] => 20250316315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => MEMORY DEVICE RELATED TO PRECHARGING A BIT LINE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/804668 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804668
MEMORY DEVICE RELATED TO PRECHARGING A BIT LINE AND METHOD OF OPERATING THE MEMORY DEVICE Aug 13, 2024 Pending
Array ( [id] => 20520164 [patent_doc_number] => 20260044270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => Power Save Mode By Disabling Multi-Channel Memory [patent_app_type] => utility [patent_app_number] => 18/799484 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18799484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/799484
Power Save Mode By Disabling Multi-Channel Memory Aug 8, 2024 Pending
Array ( [id] => 20460873 [patent_doc_number] => 20260010299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => MANAGING INITIALIZATION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/791336 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791336
MANAGING INITIALIZATION IN MEMORY DEVICES Jul 30, 2024 Pending
Array ( [id] => 20500715 [patent_doc_number] => 20260030176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => CONDENSED MEMORY-MANAGEMENT PROTECTION IN MULTI-TENANT SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/786528 [patent_app_country] => US [patent_app_date] => 2024-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786528
CONDENSED MEMORY-MANAGEMENT PROTECTION IN MULTI-TENANT SYSTEMS Jul 27, 2024 Pending
Array ( [id] => 20461055 [patent_doc_number] => 20260010483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => Memory page management method, system, and apparatus, device, and computer non-volatile readable storage medium [patent_app_type] => utility [patent_app_number] => 19/117311 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19117311 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/117311
Memory page management method, system, and apparatus, device, and computer non-volatile readable storage medium Jul 25, 2024 Issued
Array ( [id] => 20195316 [patent_doc_number] => 20250272026 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-08-28 [patent_title] => MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/771865 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771865
MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES Jul 11, 2024 Issued
Array ( [id] => 20195316 [patent_doc_number] => 20250272026 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-08-28 [patent_title] => MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/771865 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771865
MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES Jul 11, 2024 Issued
Array ( [id] => 20481658 [patent_doc_number] => 12530133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Memory device and program speed control method thereof [patent_app_type] => utility [patent_app_number] => 18/767529 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8499 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767529
Memory device and program speed control method thereof Jul 8, 2024 Issued
Array ( [id] => 20446782 [patent_doc_number] => 20260003504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => Power Gating for Memory Physical Layers [patent_app_type] => utility [patent_app_number] => 18/758387 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758387
Power Gating for Memory Physical Layers Jun 27, 2024 Pending
Array ( [id] => 20868021 [patent_doc_number] => 12694929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Dual tracking for fly bit line static random access memory (SRAM) architecture [patent_app_type] => utility [patent_app_number] => 18/756659 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756659
DUAL TRACKING FOR FLY BIT LINE STATIC RANDOM ACCESS MEMORY (SRAM) ARCHITECTURE Jun 26, 2024 Issued
Array ( [id] => 20428131 [patent_doc_number] => 20250390221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => METHODS, DEVICES AND SYSTEMS FOR SERIAL BUS OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/750629 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750629
METHODS, DEVICES AND SYSTEMS FOR SERIAL BUS OPERATIONS Jun 20, 2024 Issued
Array ( [id] => 20421702 [patent_doc_number] => 20250383787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => METHOD AND DEVICE FOR SECURING USER DATA ON A DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/747422 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747422
Method and device for securing user data on a data storage device Jun 17, 2024 Issued
Array ( [id] => 20249871 [patent_doc_number] => 20250298740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => MEMORY DEVICE, OPERATION METHOD THEREOF, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/745004 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745004 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745004
MEMORY DEVICE, OPERATION METHOD THEREOF, AND MEMORY SYSTEM Jun 16, 2024 Pending
Array ( [id] => 20145527 [patent_doc_number] => 12379869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Adjustable function-in-memory computation system [patent_app_type] => utility [patent_app_number] => 18/744351 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744351
Adjustable function-in-memory computation system Jun 13, 2024 Issued
Array ( [id] => 19481810 [patent_doc_number] => 20240329852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ADAPTIVE SCANNING OF MEMORY DEVICES WITH SUPERVISED LEARNING [patent_app_type] => utility [patent_app_number] => 18/739982 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739982 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739982
Adaptive scanning of memory devices with supervised learning Jun 10, 2024 Issued
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