Search

Zhuo H. Li

Examiner (ID: 15574, Phone: (571)272-4183 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2185, 2133, 2186, 2189
Total Applications
846
Issued Applications
701
Pending Applications
71
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20773277 [patent_doc_number] => 12656950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Tuned datapath in stacked memory device [patent_app_type] => utility [patent_app_number] => 18/736247 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/736247
Tuned datapath in stacked memory device Jun 5, 2024 Issued
Array ( [id] => 20960313 [patent_doc_number] => 12730751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-08 [patent_title] => Metadata-caching integrated circuit device [patent_app_type] => utility [patent_app_number] => 18/732777 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5480 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/732777
METADATA-CACHING INTEGRATED CIRCUIT DEVICE Jun 3, 2024 Pending
Array ( [id] => 20242706 [patent_doc_number] => 12423024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Method and device for accessing memory [patent_app_type] => utility [patent_app_number] => 18/660095 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1243 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660095
Method and device for accessing memory May 8, 2024 Issued
Array ( [id] => 20528905 [patent_doc_number] => 12547340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Multi-type disk drive support using a common server storage backplane [patent_app_type] => utility [patent_app_number] => 18/657553 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657553 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657553
Multi-type disk drive support using a common server storage backplane May 6, 2024 Issued
Array ( [id] => 19942436 [patent_doc_number] => 12314567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-27 [patent_title] => Multi-chip module (MCM) with multi-port unified memory [patent_app_type] => utility [patent_app_number] => 18/653644 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653644
Multi-chip module (MCM) with multi-port unified memory May 1, 2024 Issued
Array ( [id] => 19719301 [patent_doc_number] => 12204840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-21 [patent_title] => Multi-chip module (MCM) with multi-port unified memory [patent_app_type] => utility [patent_app_number] => 18/653661 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5970 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653661 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653661
Multi-chip module (MCM) with multi-port unified memory May 1, 2024 Issued
Array ( [id] => 19588213 [patent_doc_number] => 20240385770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => WRITING TO RERAM [patent_app_type] => utility [patent_app_number] => 18/646479 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646479
WRITING TO RERAM Apr 24, 2024 Abandoned
Array ( [id] => 20550488 [patent_doc_number] => 12561281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Reducing stable data eviction with synthetic baseline snapshot and eviction state refresh [patent_app_type] => utility [patent_app_number] => 18/641602 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641602 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641602
Reducing stable data eviction with synthetic baseline snapshot and eviction state refresh Apr 21, 2024 Issued
Array ( [id] => 20160112 [patent_doc_number] => 12386740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Data storage device, operation method thereof, and storage system including the same [patent_app_type] => utility [patent_app_number] => 18/626328 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 1055 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626328
Data storage device, operation method thereof, and storage system including the same Apr 3, 2024 Issued
Array ( [id] => 20281557 [patent_doc_number] => 20250306799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => LOW LATENCY SCRATCH MEMORY PATH [patent_app_type] => utility [patent_app_number] => 18/619513 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619513
LOW LATENCY SCRATCH MEMORY PATH Mar 27, 2024 Pending
Array ( [id] => 19499132 [patent_doc_number] => 20240338150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => APPARATUS, SYSTEM, AND METHOD OF DATA ARRAY TRANSFORMATION [patent_app_type] => utility [patent_app_number] => 18/608688 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608688
APPARATUS, SYSTEM, AND METHOD OF DATA ARRAY TRANSFORMATION Mar 17, 2024 Pending
Array ( [id] => 21012046 [patent_doc_number] => 12748528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-29 [patent_title] => Method and circuit for reducing processing latency [patent_app_type] => utility [patent_app_number] => 18/591662 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591662
METHOD AND CIRCUIT FOR REDUCING PROCESSING LATENCY Feb 28, 2024 Pending
Array ( [id] => 20195300 [patent_doc_number] => 20250272010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY DEVICE BACKGROUND OPERATION MANAGEMENT FOR LOW HOST BATTERY [patent_app_type] => utility [patent_app_number] => 18/584516 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584516
Memory device background operation management for low host battery Feb 21, 2024 Issued
Array ( [id] => 19405761 [patent_doc_number] => 20240289272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SYSTEMS AND TECHNIQUES FOR UPDATING LOGICAL-TO-PHYSICAL MAPPINGS [patent_app_type] => utility [patent_app_number] => 18/444421 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444421
SYSTEMS AND TECHNIQUES FOR UPDATING LOGICAL-TO-PHYSICAL MAPPINGS Feb 15, 2024 Pending
Array ( [id] => 19452415 [patent_doc_number] => 20240312545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => EFUSE UNIT AND APPLICATION CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 18/440635 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440635
Efuse unit and application circuit thereof Feb 12, 2024 Issued
Array ( [id] => 20434299 [patent_doc_number] => 12505034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Memory system and operation method thereof [patent_app_type] => utility [patent_app_number] => 18/437333 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437333
Memory system and operation method thereof Feb 8, 2024 Issued
Array ( [id] => 19189743 [patent_doc_number] => 20240168656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => MEMORY ARRAY ACCESSIBILITY [patent_app_type] => utility [patent_app_number] => 18/425725 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425725
Memory array accessibility Jan 28, 2024 Issued
Array ( [id] => 20137837 [patent_doc_number] => 20250244881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => DYNAMIC SENSING SCHEME TO COMPENSATE FOR THRESHOLD VOLTAGE SHIFT DURING SENSING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/423474 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423474
Dynamic sensing scheme to compensate for threshold voltage shift during sensing in a memory device Jan 25, 2024 Issued
Array ( [id] => 19678177 [patent_doc_number] => 12190038 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-07 [patent_title] => Multi-chip module (MCM) with multi-port unified memory [patent_app_type] => utility [patent_app_number] => 18/420006 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5824 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420006
Multi-chip module (MCM) with multi-port unified memory Jan 22, 2024 Issued
Array ( [id] => 20440228 [patent_doc_number] => 12511064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => High-performance, high-capacity memory modules and systems [patent_app_type] => utility [patent_app_number] => 18/419933 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 3295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419933
High-performance, high-capacity memory modules and systems Jan 22, 2024 Issued
Menu