Search

Zhuo H. Li

Examiner (ID: 15574, Phone: (571)272-4183 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2185, 2133, 2186, 2189
Total Applications
846
Issued Applications
701
Pending Applications
71
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19811332 [patent_doc_number] => 12242726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Capability messaging for memory operations across banks with multiple page access [patent_app_type] => utility [patent_app_number] => 17/892539 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 19235 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892539
Capability messaging for memory operations across banks with multiple page access Aug 21, 2022 Issued
Array ( [id] => 20556885 [patent_doc_number] => 20260056669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => SELECTABLE ERROR HANDLING MODES IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 19/103773 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19103773 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/103773
SELECTABLE ERROR HANDLING MODES IN MEMORY SYSTEMS Aug 15, 2022 Pending
Array ( [id] => 19514049 [patent_doc_number] => 20240345735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH DEDICATED READ-WRITE DATA PATHS [patent_app_type] => utility [patent_app_number] => 18/681716 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18681716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/681716
Low latency dynamic random access memory (DRAM) architecture with dedicated read-write data paths Aug 7, 2022 Issued
Array ( [id] => 18007109 [patent_doc_number] => 20220365875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => EFFICIENT DATA STORAGE BY GROUPING SIMILAR DATA WITHIN A ZONE [patent_app_type] => utility [patent_app_number] => 17/877737 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877737
Efficient data storage by grouping similar data within a zone Jul 28, 2022 Issued
Array ( [id] => 18925240 [patent_doc_number] => 20240028244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => METHODS OF OPERATING MEMORY SYSTEMS WITH INPUT/OUTPUT EXPANDERS FOR MULTI-CHANNEL STATUS READS, AND ASSOCIATED SYSTEMS AND DEVICES [patent_app_type] => utility [patent_app_number] => 17/873046 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873046
METHODS OF OPERATING MEMORY SYSTEMS WITH INPUT/OUTPUT EXPANDERS FOR MULTI-CHANNEL STATUS READS, AND ASSOCIATED SYSTEMS AND DEVICES Jul 24, 2022 Pending
Array ( [id] => 18949659 [patent_doc_number] => 11892952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => No-locality hint vector memory access processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 17/867673 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 25212 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867673
No-locality hint vector memory access processors, methods, systems, and instructions Jul 17, 2022 Issued
Array ( [id] => 18663202 [patent_doc_number] => 20230309227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => COMPRESSION ATTACHED MEMORY MODULE (CAMM) FOR LOW-POWER DOUBLE DATA RAGE (LPDDR) MEMORIES [patent_app_type] => utility [patent_app_number] => 17/861856 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861856
Compression attached memory module (CAMM) for low-power double data rate (LPDDR) memories Jul 10, 2022 Issued
Array ( [id] => 17962027 [patent_doc_number] => 20220342608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => Controller for Quality Of Service Based Arbitrations [patent_app_type] => utility [patent_app_number] => 17/860318 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860318
Controller for quality of service based arbitrations Jul 7, 2022 Issued
Array ( [id] => 17962026 [patent_doc_number] => 20220342607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => Controller for Quality Of Service Based Arbitrations [patent_app_type] => utility [patent_app_number] => 17/860203 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860203 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860203
Controller for quality of service based arbitrations Jul 7, 2022 Issued
Array ( [id] => 18531681 [patent_doc_number] => 20230236753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => PREDICTIVE SANITIZATION OF AN ARRAY OF MEMORY WITH CAPACITIVE CELLS AND/OR FERROELECTRIC CELLS [patent_app_type] => utility [patent_app_number] => 17/854639 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854639
Predictive sanitization of an array of memory with capacitive cells and/or ferroelectric cells Jun 29, 2022 Issued
Array ( [id] => 17947944 [patent_doc_number] => 20220334963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => MEMORY ACCESS TRACING [patent_app_type] => utility [patent_app_number] => 17/849387 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849387
Memory access tracing Jun 23, 2022 Issued
Array ( [id] => 17884946 [patent_doc_number] => 20220300423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MEMORY MANAGEMENT IN A MULTIPLE PROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 17/806419 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806419 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806419
Memory management in a multiple processor system Jun 9, 2022 Issued
Array ( [id] => 18330797 [patent_doc_number] => 11636039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Mapping for multi-state programming of memory devices [patent_app_type] => utility [patent_app_number] => 17/746849 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746849
Mapping for multi-state programming of memory devices May 16, 2022 Issued
Array ( [id] => 18006946 [patent_doc_number] => 20220365712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD AND DEVICE FOR ACCESSING MEMORY [patent_app_type] => utility [patent_app_number] => 17/741187 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741187 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741187
Method and device for accessing memory May 9, 2022 Issued
Array ( [id] => 18765638 [patent_doc_number] => 11816036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Method and system for performing data movement operations with read snapshot and in place write update [patent_app_type] => utility [patent_app_number] => 17/738919 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 17739 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738919
Method and system for performing data movement operations with read snapshot and in place write update May 5, 2022 Issued
Array ( [id] => 18294111 [patent_doc_number] => 20230103797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/724081 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724081
Memory controller and method of operating the same Apr 18, 2022 Issued
Array ( [id] => 17763297 [patent_doc_number] => 20220236909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Neural Network Computing Chip and Computing Method [patent_app_type] => utility [patent_app_number] => 17/722890 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722890
Neural network computing chip and computing method Apr 17, 2022 Issued
Array ( [id] => 18677687 [patent_doc_number] => 20230315333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => REDUCED DATA REPRESENTATION MEMORY CONTROLLER AND RELATED CHIPLET SETS [patent_app_type] => utility [patent_app_number] => 17/712137 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712137
Reduced data representation memory controller and related chiplet sets Apr 1, 2022 Issued
Array ( [id] => 19015100 [patent_doc_number] => 11922032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-05 [patent_title] => Content relocation and hash updates in algorithmic TCAM [patent_app_type] => utility [patent_app_number] => 17/710798 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6006 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710798 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710798
Content relocation and hash updates in algorithmic TCAM Mar 30, 2022 Issued
Array ( [id] => 18659729 [patent_doc_number] => 20230305736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => COMPRESSION ATTACHED MEMORY MODULE (CAMM) FOR LOW-POWER DOUBLE DATA RATE (LPDDR) MEMORIES [patent_app_type] => utility [patent_app_number] => 17/656662 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656662
Compression attached memory module (CAMM) for low-power double data rate (LPDDR) memories Mar 27, 2022 Issued
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