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Zubair Ahmed

Examiner (ID: 19591, Phone: (571)272-1655 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2132
Total Applications
673
Issued Applications
444
Pending Applications
70
Abandoned Applications
174

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20557100 [patent_doc_number] => 20260056886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => DYNAMIC EXTENSION OF CACHE COHERENCE SNOOP FILTER ENTRY [patent_app_type] => utility [patent_app_number] => 19/283953 [patent_app_country] => US [patent_app_date] => 2025-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19283953 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/283953
DYNAMIC EXTENSION OF CACHE COHERENCE SNOOP FILTER ENTRY Jul 28, 2025 Pending
Array ( [id] => 20338005 [patent_doc_number] => 20250342125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => MEMORY CONTROLLER FOR RPMB-INCLUSIVE MEMORY DEVICE, OPERATING METHOD THEREOF AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 19/266176 [patent_app_country] => US [patent_app_date] => 2025-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19266176 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/266176
MEMORY CONTROLLER FOR RPMB-INCLUSIVE MEMORY DEVICE, OPERATING METHOD THEREOF AND ELECTRONIC DEVICE INCLUDING THE SAME Jul 10, 2025 Pending
Array ( [id] => 20446789 [patent_doc_number] => 20260003511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY SYSTEM LOGICAL UNIT NUMBER PROCEDURES [patent_app_type] => utility [patent_app_number] => 19/263143 [patent_app_country] => US [patent_app_date] => 2025-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19263143 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/263143
MEMORY SYSTEM LOGICAL UNIT NUMBER PROCEDURES Jul 7, 2025 Pending
Array ( [id] => 20446797 [patent_doc_number] => 20260003519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => CONTROL LOGIC IN A MEMORY DEVICE FOR GENERATING INTERNAL COMMANDS [patent_app_type] => utility [patent_app_number] => 19/244301 [patent_app_country] => US [patent_app_date] => 2025-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19244301 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/244301
CONTROL LOGIC IN A MEMORY DEVICE FOR GENERATING INTERNAL COMMANDS Jun 19, 2025 Pending
Array ( [id] => 20428150 [patent_doc_number] => 20250390240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => APPARATUS WITH PROCESSING LEVEL CALIBRATION MECHANISM AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 19/222965 [patent_app_country] => US [patent_app_date] => 2025-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19222965 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/222965
APPARATUS WITH PROCESSING LEVEL CALIBRATION MECHANISM AND METHODS FOR OPERATING THE SAME May 28, 2025 Pending
Array ( [id] => 20421720 [patent_doc_number] => 20250383805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => DIVIDING SUPERBLOCKS IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 19/222891 [patent_app_country] => US [patent_app_date] => 2025-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19222891 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/222891
DIVIDING SUPERBLOCKS IN A MEMORY SYSTEM May 28, 2025 Pending
Array ( [id] => 20365998 [patent_doc_number] => 20250355810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => COMPUTING DEVICE WITH CACHE MEMORY OPTIMIZED FOR MATRIX COMPUTING [patent_app_type] => utility [patent_app_number] => 19/204516 [patent_app_country] => US [patent_app_date] => 2025-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19204516 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/204516
COMPUTING DEVICE WITH CACHE MEMORY OPTIMIZED FOR MATRIX COMPUTING May 9, 2025 Pending
Array ( [id] => 20061748 [patent_doc_number] => 20250199970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY [patent_app_type] => utility [patent_app_number] => 19/072570 [patent_app_country] => US [patent_app_date] => 2025-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19072570 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/072570
MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY Mar 5, 2025 Pending
Array ( [id] => 20249843 [patent_doc_number] => 20250298712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => PROGRAMMABLE PROCESSOR FOR MEMORY TELEMETRY [patent_app_type] => utility [patent_app_number] => 19/071422 [patent_app_country] => US [patent_app_date] => 2025-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19071422 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/071422
PROGRAMMABLE PROCESSOR FOR MEMORY TELEMETRY Mar 4, 2025 Pending
Array ( [id] => 20061502 [patent_doc_number] => 20250199724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => Dynamic Memory Address Write Policy Translation based on Performance Needs [patent_app_type] => utility [patent_app_number] => 19/070991 [patent_app_country] => US [patent_app_date] => 2025-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19070991 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/070991
Dynamic Memory Address Write Policy Translation based on Performance Needs Mar 4, 2025 Pending
Array ( [id] => 20035007 [patent_doc_number] => 20250173229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => PERSISTENT MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 19/038216 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038216 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/038216
PERSISTENT MEMORY ARCHITECTURE Jan 26, 2025 Pending
Array ( [id] => 20897906 [patent_doc_number] => 12705172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-11 [patent_title] => Memory controller for performing read operation and operating method thereof [patent_app_type] => utility [patent_app_number] => 19/036903 [patent_app_country] => US [patent_app_date] => 2025-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19036903 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/036903
MEMORY CONTROLLER FOR PERFORMING READ OPERATION AND OPERATING METHOD THEREOF Jan 23, 2025 Pending
Array ( [id] => 20017849 [patent_doc_number] => 20250156071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => UNDERFILL DETECTION FOR MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 19/022802 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022802 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/022802
UNDERFILL DETECTION FOR MEMORY SYSTEMS Jan 14, 2025 Pending
Array ( [id] => 20009479 [patent_doc_number] => 20250147701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SPECIFYING MEDIA TYPE IN WRITE COMMANDS [patent_app_type] => utility [patent_app_number] => 19/017955 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017955 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/017955
SPECIFYING MEDIA TYPE IN WRITE COMMANDS Jan 12, 2025 Pending
Array ( [id] => 20009437 [patent_doc_number] => 20250147659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => 3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC [patent_app_type] => utility [patent_app_number] => 19/016833 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19016833 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/016833
3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC Jan 9, 2025 Pending
Array ( [id] => 20428358 [patent_doc_number] => 20250390450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => MEMORY MODULE HAVING SYNCHRONOUS ARBITRATOR AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 19/011154 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19011154 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/011154
MEMORY MODULE HAVING SYNCHRONOUS ARBITRATOR AND METHOD OF OPERATING THE SAME Jan 5, 2025 Pending
Array ( [id] => 20365756 [patent_doc_number] => 20250355568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MEMORY APPARATUS AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/010858 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19010858 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/010858
MEMORY APPARATUS AND OPERATION METHOD THEREOF Jan 5, 2025 Pending
Array ( [id] => 20474962 [patent_doc_number] => 20260017183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => CONTROLLER AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 19/009251 [patent_app_country] => US [patent_app_date] => 2025-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19009251 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/009251
CONTROLLER AND STORAGE DEVICE Jan 2, 2025 Pending
Array ( [id] => 20070780 [patent_doc_number] => 20250209002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => MANAGEMENT OF MULTIPLE CACHE LINE INVALIDATIONS [patent_app_type] => utility [patent_app_number] => 18/990505 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18990505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/990505
MANAGEMENT OF MULTIPLE CACHE LINE INVALIDATIONS Dec 19, 2024 Pending
Array ( [id] => 19892024 [patent_doc_number] => 20250117336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => DATA ACCESS IN A HETEROGENEOUS PROCESSING SYSTEM WITH MULTIPLE PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/984852 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984852
DATA ACCESS IN A HETEROGENEOUS PROCESSING SYSTEM WITH MULTIPLE PROCESSORS Dec 16, 2024 Pending
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