Date Field | Doc. No. | Party | Description |
---|
Mar 4, 2020 | 28 | | Patent Owner's Notice of Appeal Download |
Jan 6, 2020 | 27 | | Termination Decision Document Download |
Nov 6, 2019 | 26 | | Hearing Transcript Download |
Oct 7, 2019 | 1020 | | Petitioner's Demonstratives Download |
Oct 7, 2019 | 25 | | Petitioner's Updated Exhibit List Download |
Oct 7, 2019 | 24 | | Patent Owner's Demonstrative Exhibits Download |
Sep 30, 2019 | 23 | | Petitioner's Reply To Patent Owner's Opposition To Petitioner's Motion To Exclude Evidence Download |
Sep 24, 2019 | 22 | | Oral Hearing
35 U.S.C. sec 316(a)(10) and 37 C.F.R. sec 42.70 Download |
Sep 23, 2019 | 21 | | Patent Owner's Opposition to Petitioner's Motion to Exclude Evidence Download |
Sep 16, 2019 | 18 | | Patent Owner's Request for Oral Argument Download |
Sep 16, 2019 | 19 | | Motion to Exclude Evidence Download |
Sep 16, 2019 | 20 | | Petitioner's Request for Oral Argument Download |
Aug 15, 2019 | 2006 | | Ex 2006 - Second Horst Depo Transcript Download |
Aug 15, 2019 | 17 | | Patent Owner Sur-Reply Download |
Jul 24, 2019 | 16 | | Notice of Deposition of Robert Horst Download |
Jul 15, 2019 | 15 | | Petitioner's Reply to Patent Owner's Response Download |
Jul 15, 2019 | 1019 | | Pedram Deposition Transcript Download |
Jul 15, 2019 | 1018 | | N. Mohyuddin, K. Patel, and M. Pedram - Deterministic clock
gating to eliminate wasteful activity in out-of-order superscalar
processors due to wrong-path instructions Download |
Jul 15, 2019 | 1017 | | M. Pedram - Design technologies for Low Power VLSI Download |
Jul 15, 2019 | 1016 | | U.S. Patent No. 4,922,461 (Hayakawa) Download |
Jul 15, 2019 | 1015 | | Modern Dictionary of Electronics Download |
Jul 15, 2019 | 1014 | | IEEE Dictionary (with additional page) Download |
Jul 15, 2019 | 1013 | | Second Declaration of Dr. Robert Horst, Ph.D Download |
May 16, 2019 | 14 | | Petitioner's Updated Mandatory Notices Download |
May 15, 2019 | 13 | | Notice of Deposition Download |
Apr 22, 2019 | 12 | | Petitioner's Objections to Evidence Download |
Apr 15, 2019 | 2003 | | Ex 2003 - Itoh (additional portions) Download |
Apr 15, 2019 | 2005 | | Ex 2005 - Horst depo transcript Download |
Apr 15, 2019 | 2004 | | Ex 2004 - Alpert declaration Download |
Apr 15, 2019 | 11 | | Patent Owner Response Download |
Apr 15, 2019 | 2002 | | Ex 2002 - IEEE Dictionary Download |
Apr 15, 2019 | 2001 | | Ex 2001 - Pedram declaration Download |
Mar 8, 2019 | 10 | | Patent Owner's Updated Mandatory Notices Download |
Mar 5, 2019 | 9 | | Petitioner's Updated Mandatory Notices Download |
Feb 13, 2019 | 8 | | Notice of Deposition of Dr. Horst Download |
Jan 15, 2019 | 7 | | Scheduling Order Download |
Jan 15, 2019 | 6 | | Trial Instituted Document Download |
Jul 17, 2018 | 5 | | Notice of Accord Filing Date Download |
Jul 9, 2018 | 4 | | Patent Owner's Power of Attorney Download |
Jul 9, 2018 | 3 | | Patent Owner's Mandatory Notices Download |
Jun 18, 2018 | 1006 | | U.S. Patent Pub. No. 2006/0098520 to Toru Asano et al Download |
Jun 18, 2018 | 1005 | | U.S. Patent No. 4,951,259 to Yoichi Sato Download |
Jun 18, 2018 | 1001 | | U.S. Patent No. 7,693,002 to Jentsung Lin Download |
Jun 18, 2018 | 1002 | | Prosecution History of the 002 patent Download |
Jun 18, 2018 | 1011 | | U.S. Patent No. 6,483,771 to Tae jeen Shin Download |
Jun 18, 2018 | 1004 | | Curriculum Vitae of Dr. Horst Download |
Jun 18, 2018 | 1010 | | Declaration of Edward Faeth Download |
Jun 18, 2018 | 1003 | | Declaration of Dr. Robert Horst, Ph.D Download |
Jun 18, 2018 | 1007 | | Kiyoo Itoh, VLSI Memory Chip Design, (Springer 2001) Download |
Jun 18, 2018 | 1 | | Petitioner's Power of Attorney Download |
Jun 18, 2018 | 2 | | Petition for Inter Partes Review Download |
Jun 18, 2018 | 1008 | | U.S. Patent No. 5,291,076 to Jeffrey T. Bridges Download |
Jun 18, 2018 | 1012 | | U.S. Patent No. 5,602,796 to Kenichiro Sugio Download |
Jun 18, 2018 | 1009 | | Stephen Brown et al., Fundamentals of Digital Logic with Verilog Design, (McGraw Hill 2003) Download |