Case number IPR2019-00834
Intel Corporation v. Institute of Microelectronics, Chinese Academy of Sciences > Documents
| Date Field | Doc. No. | Party | Description |
|---|---|---|---|
| Jun 19, 2020 | 14 | board | Download |
| Apr 8, 2020 | 13 | Petitioners Updated Mandatory Notice Download | |
| Nov 4, 2019 | 12 | Petitioner's Request for Rehearing Download | |
| Oct 4, 2019 | 11 | Decision Denying Institution Download | |
| Aug 2, 2019 | 10 | Patent Owner's Updated Exhibit List Download | |
| Aug 2, 2019 | 2032 | Declaration of Etai Lahav in Support of Patent Owner's Motion for Pro Hac Vice Admission Download | |
| Aug 2, 2019 | 9 | Download | |
| Aug 1, 2019 | 8 | Petitioner's Motion for Pro Hac Vice Admission of C. Campbell and Updated Exhibit List Download | |
| Aug 1, 2019 | 1041 | Ex. 1041 - Certified English Translation of Pat. Pub. No. PCT2008114341 Download | |
| Aug 1, 2019 | 1041 | Ex. 1041 - Certified English Translation of Pat. Pub. No. PCT2008114341 Download | |
| Aug 1, 2019 | 1062 | Affidavit in Support of Petitioner's Motion for Pro Hac Vice Admission of C. Campbell Download | |
| Jul 10, 2019 | 2023 | U.S. Patent No. 5,651,857 Download | |
| Jul 10, 2019 | 2030 | Certified English Translation of Int¿¿¿l Pub. No. WO 2008/114341 (¿¿¿Okuno PCT¿¿¿) Download | |
| Jul 10, 2019 | 2029 | Denial of Intel Corp. (China)¿¿¿s Invalidation Request Against CN201110240931.5, dated February 3, 2019. Download | |
| Jul 10, 2019 | 7 | Patent Owner's Exhibit List Download | |
| Jul 10, 2019 | 2019 | FINFET EXTENDING MOORE¿¿¿S LAW (LexInnova, 2015) Download | |
| Jul 10, 2019 | 2022 | U.S. Patent Application Pub. No. 2012/0329220 Download | |
| Jul 10, 2019 | 2025 | Intel Corporation v. Institute of Microelectronics, Chinese Academy of Sciences, IPR2018-01574, Paper No. 18 (P.T.A.B. Mar. 29, 2019) Download | |
| Jul 10, 2019 | 2031 | Machine Translation of JP 2008/114341 provided by Japan Platform for Patent Information Download | |
| Jul 10, 2019 | 2027 | Intel Corp. (China)¿¿¿s Invalidation Request Against CN201110240931.5, dated March 26, 2018. Download | |
| Jul 10, 2019 | 2028 | Notice of Transmission of Intel Corp. (China)¿¿¿s Memorandum in Support of the Invalidation Request Against CN201110240931.5, dated May 8, 2018. Download | |
| Jul 10, 2019 | 2021 | U.S. Patent No. 6,797,593 Download | |
| Jul 10, 2019 | 2017 | Huaxiang Yin & Qiuxia Xu, Design Considerations of the Sub-50nm Self-Aligned Double Gate MOSFET with a New Channel Doping Profile, 2001 6TH INT¿¿¿L CONF. ON SOLID-STATE AND INTEGRATED CIRCUIT TECH. PROC. (Cat. No.01EX443), Shanghai, China, 535-538 (2001) Download | |
| Jul 10, 2019 | 2018 | Huaxiang Yin & Qiuxia Xu, CMOS FinFET Fabricated on Bulk Silicon Substrate, 24 CHINESE J. OF SEMICONDUCTORS 4 (Apr. 2003) Download | |
| Jul 10, 2019 | 2024 | Email correspondence from McFarland to the Patent Trial and Appeal Board, dated February 20, 2019. Download | |
| Jul 10, 2019 | 2020 | Excerpt from MERRIAM-WEBSTER¿¿¿S COLLEGIATE DICTIONARY (11th ed. 2006) Download | |
| Jul 10, 2019 | 6 | Patent Owner's Preliminary Response Download | |
| Jul 10, 2019 | 2026 | Email correspondence from the Patent Trial and Appeal Board to McFarland, dated March 25, 2019. Download | |
| Jul 10, 2019 | 2003 | Prof. Tsu-Jae King Liu, Planar Bulk CMOS Scaling to the End of the Road (Nov. 2012) Download | |
| Jul 10, 2019 | 2016 | Bin Yu, et. al., FinFET scaling to 10 nm gate length, IEEE ELECTRON DEVICES MEETING (2002) Download | |
| Jul 10, 2019 | 2010 | H. Kawasaki, et. al., Challenges and Solution of FinFET Integration in an SRAM Cell and Logic Circuit for 22nm node and beyond, IEEE ELECTRON DEVICES MEETING (2009) Download | |
| Jul 10, 2019 | 2015 | Daewon Ha, et. al., Molybdenum Gate Hfo/Sub 2/ CMOS Finfet Technology, IEEE ELECTRON DEVICES MEETING (2004) Download | |
| Jul 10, 2019 | 2012 | Nick Lindert, et. al., Sub-60-nm quasi-planar FinFETs fabricated using a simplified process, 22 IEEE ELECTRON DEVICE LETTERS, 487-489 (Oct. 2001) Download | |
| Jul 10, 2019 | 2006 | P. Packan, et. al., High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors, IEEE ELECTRON DEVICES MEETING (2009) Download | |
| Jul 10, 2019 | 2004 | T. Ghani, et. al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS transistors, IEEE ELECTRON DEVICES MEETING (2003) Download | |
| Jul 10, 2019 | 2005 | S. Tyagi, et. al., An Advanced Low Power, High Performance, Strained Channel 65nm Technology, IEEE ELECTRON DEVICES MEETING (2005) Download | |
| Jul 10, 2019 | 2011 | U.S. Patent No. 7,402,856 Download | |
| Jul 10, 2019 | 2009 | Xuejue Huang, et. al., Sub-50 nm P-channel FinFET, 48 IEEE TRANSACTIONS ON ELECTRON DEVICES, 880-886 (May 2001) Download | |
| Jul 10, 2019 | 2007 | Edward J. Nowak, et al., Turning Silicon On Its Edge [double gate CMOS/FinFET technology], 20 IEEE CIRCUITS & DEVICES MAG. 20-31 (2004) Download | |
| Jul 10, 2019 | 2013 | Yang-kyu Choi, et. al., FinFET process refinements for improved mobility and gate work function engineering, IEEE ELECTRON DEVICES MEETING, 259-262 (Dec. 2002) Download | |
| Jul 10, 2019 | 2008 | Digh Hisamoto, et. al., A Folded-channel MOSFET for Deep-sub-tenth Micron Era, IEEE ELECTRON DEVICES MEETING (1998) Download | |
| Jul 10, 2019 | 2014 | C. H. Lee, et. al., Novel Body Tied Finfet Cell Array Transistor DRAM With Negative Word Line Operation For Sub 60nm Technology And Beyond, IEEE SYMP. ON VLSI TECH. DIG. OF TECHNICAL PAPERS (2004) Download | |
| Jul 10, 2019 | 2002 | Bill Dally, Life After Moore¿¿¿s Law, Apr. 29, 2010, available at https://www.forbes.com/2010/04/29/moores-law-computing-processing-opinions-contributors-bill-dally.html#7ce473c82a86 Download | |
| Apr 10, 2019 | 5 | Notice of Accord Filing Date Download | |
| Apr 9, 2019 | 3 | Patent Owner's Mandatory Notice Download | |
| Apr 9, 2019 | 4 | Patent Owner's Power of Attorney Download | |
| Mar 19, 2019 | 1049 | Alan G. Lewis & John Y. Chen, VLSI ELECTRONICS MICROSTRUCTURE SCIENCE - Vol 18: Advanced MOS Device Physics 37-117 (Academic Press 1989) ("Lewis") Download | |
| Mar 19, 2019 | 1014 | Chinese Patent No. 102956457B Download | |
| Mar 19, 2019 | 1035 | Z. Guo et al., FinFET-based SRAM design, Proceedings of the 2005 International Symposium on Low Power Electronics and Design 2-7 (2005) ("Guo") Download | |
| Mar 19, 2019 | 1019 | Jack Kavalieros et al., Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, 2006 IEEE Symposium on VLSI Technology Digest of Technical Papers (2006) ("Kavalieros") Download | |
| Mar 19, 2019 | 1010 | U.S. Patent Application Pub. No. 2006/0175669 ("Kim") Download | |
| Mar 19, 2019 | 1053 | Cheng-Tung Huang et al., New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer, 46 Jpn. J. Appl. Phys., 2015-2018 (2007) ("Huang 2007") Download | |
| Mar 19, 2019 | 1054 | K. Sukegawa et al., Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform, 2007 IEEE Symposium on VLSI Technology, 174-175 (2007) ("Sukegawa") Download | |
| Mar 19, 2019 | 1 | PETITION FOR INTER PARTES REVIEW F U.S. PATENT NO. 9,070,719 B2 Claims 1-3, 6-7 Download | |
| Mar 19, 2019 | 1032 | U.S. Patent Application Pub. No. 2007/0284671 ("Tsutsumi") Download | |
| Mar 19, 2019 | 1028 | U.S. Patent No. 6,413,802 ("Hu") Download | |
| Mar 19, 2019 | 1060 | Digh Hisamoto et al., A Folded-channel MOSFET for Deep-sub-tenth Micron Era, International Electron Devices Meeting, 1032-1034 (1998) ("Hisamoto") Download | |
| Mar 19, 2019 | 1030 | S. Natarajan, et al., A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors Enhanced Channel Strain and 0.171µm2 SRAM Cell Size in a 291Mb Array, IEEE Electron Devices Meeting (2008) ("Natarajan") Download | |
| Mar 19, 2019 | 1055 | Badih El-Kareh, Silicon Devices and Process Integration, Deep Submicron and Nano-Scale Technologies, 439-446 (Springer 2009) ("El-Kareh") Download | |
| Mar 19, 2019 | 1012 | U.S. Patent No. 9,293,377 (the " '377 patent") Download | |
| Mar 19, 2019 | 1044 | Intel Corp. v. Alacritech, Inc., IPR2018-00226, Paper 7 (PTAB June 5, 2018) Download | |
| Mar 19, 2019 | 1026 | U.S. Patent Application Pub. No. 2011/0068411 ("Sun") Download | |
| Mar 19, 2019 | 1017 | Intel Technology Journal Vol. 12, Issue 2, 77-86, 121-130 (June 17, 2008) ("Intel Technology Journal") Download | |
| Mar 19, 2019 | 1006 | U.S. Patent Application Pub. No. 2008/0251934 ("Mandelman") Download | |
| Mar 19, 2019 | 1043 | Agilent Techs., Inc. v. Thermo Fisher Sci. Inc., IPR2018-00313, Paper 23 (PTAB June 18, 2018) Download | |
| Mar 19, 2019 | 1016 | Mike Smayling, Gridded Design Rules-1 D Approach Enables Scaling of CMOS Logic, 6 Nanochip Technology Journal, 33-37 (2008) ("Nanochip Technology Journal") Download | |
| Mar 19, 2019 | 1031 | U.S. Patent No. 7,838,373 ("Giles") Download | |
| Mar 19, 2019 | 1034 | Brian Doyle et al., Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout, 2003 Symposium on VLSI Technology, Digest of Technical Papers 133-134 (2003) ("Doyle 2003") Download | |
| Mar 19, 2019 | 1023 | U.S. Patent Application Pub. No. 2007/0138559 ("Bohr") Download | |
| Mar 19, 2019 | 1061 | 2001 International Technology Roadmap for Semiconductors - Front End Processes, Semiconductor Industry Association (2001) ("2001 ITRS") Download | |
| Mar 19, 2019 | 1056 | Jakub Kedzierski et al., High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices, International Electron Devices Meeting, 437-440 (2001) ("Kedzierski") Download | |
| Mar 19, 2019 | 1018 | Linda Geppert, The Amazing Vanishing Transistor Act, IEEE Spectrum, 28-33 (Oct. 2002) ("Geppert") Download | |
| Mar 19, 2019 | 2 | Power of Attorney Download | |
| Mar 19, 2019 | 1020 | U.S. Patent No. 7,524,727 ("Dewey") Download | |
| Mar 19, 2019 | 1022 | A. Chatterjee et al., Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process, 1997 International Electron Devices Meeting Tech. Dig. 821-824 (Dec. 7-10, 1997) ("Chatterjee") Download | |
| Mar 19, 2019 | 1004 | U.S. Patent No. 7,335,583 ("Chang") Download | |
| Mar 19, 2019 | 1052 | Paul J. Tsang et al., Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology, 17 IEEE Journal of Solid-State Circuits, 220-226 (April 1982) ("Tsang") Download | |
| Mar 19, 2019 | 1015 | U.S. Patent No. 7,531,437 ("Brask") Download | |
| Mar 19, 2019 | 1047 | Stanley Wolf, Silicon Processing for the VLSI Era - Vol 2: Process Integration 298-367 (Lattice Press 1990) ("Wolf 1990") Download | |
| Mar 19, 2019 | 1001 | U.S. Patent No. 9,070,719 Download | |
| Mar 19, 2019 | 1009 | H. Iwai, Roadmap for 22 nm and beyond, 86 Microelectronic Engineering, 1520-1528 (2009) ("Iwai") Download | |
| Mar 19, 2019 | 1040 | WO International Patent Pub. No. 2008/114341 ("Okuno PCT (Japanese)") Download | |
| Mar 19, 2019 | 1042 | Gen. Plastic Indus. Co. v. Canon Kabushiki Kaisha, IPR2016-01357, Paper 19 (PTAB Sept. 6, 2017) Download | |
| Mar 19, 2019 | 1008 | U.S. Patent Application Pub. No. 2006/0024940 ("Furukawa") Download | |
| Mar 19, 2019 | 1021 | K. Mistry et al., A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, 2007 International Electron Devices Meeting Tech. Dig. 247-250 (2007) ("Mistry") Download | |
| Mar 19, 2019 | 1027 | Scott E. Thompson, et. al., A 90-nm Logic Technology Featuring Strained-Silicon, 51 IEEE Tran. Electron Devices, 1790-1797 (Nov. 2004) ("Thompson") Download | |
| Mar 19, 2019 | 1048 | Michael Quirk & Julian Serda, Semiconductor Manufacturing Technology 21-42, 199-224, 257-298, 475-514, 634 (Prentice Hall 2001) ("Quirk") Download | |
| Mar 19, 2019 | 1003 | U.S. Patent No. 9,362,290 Download | |
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| Mar 19, 2019 | 1011 | U.S. Patent No. 8,278,175 ("Cheng '175") Download | |
| Mar 19, 2019 | 1037 | Kelin J. Kuhn et al., Process technology variation, IEEE Transactions on Electron Devices 58.8 (2011) 2197-2208 ("Kuhn") Download | |
| Mar 19, 2019 | 1045 | DECLARATION OF DR. SCOTT THOMPSON IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 9,070,719 Download | |
| Mar 19, 2019 | 1059 | Xuejue Huang et al., Sub 50-nm FinFET: PMOS, International Electron Devices Meeting, 67-70 (1999) ("Huang 1999") Download | |
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| Mar 19, 2019 | 1029 | U.S. Patent Application Pub. No. 2011/0147831 ("Steigerwald") Download | |
| Mar 19, 2019 | 1046 | Stanley Wolf, Silicon Processing for the VLSI Era - Vol 4: Deep-Submicron Process Tech. 1-16, 181-226 (Lattice Press 2002) ("Wolf 2002") Download | |
| Mar 19, 2019 | 1013 | U.S. Patent Application Pub. No. 2007/0152266 ("Doyle") Download | |
| Mar 19, 2019 | 1058 | Jean-Pierre Colinge, FinFETs and Other Multi-Gate Transistors, 49-111 (Springer 2008) ("Colinge") Download | |
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| Mar 19, 2019 | 1057 | Mayank Shrivastava et al., Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines, IEEE Transactions on Electron Devices, 1597-1607 (June 2011) ("Shrivastava") Download | |
| Mar 19, 2019 | 1024 | U.S. Patent No. 5,960,270 ("Misra") Download | |
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| Mar 19, 2019 | 1033 | Mark Bohr and Kaizad Mistry, Intel's Revolutionary 22nm Transistor Technology, last visited August 27, 2018 ("Intel 22nm May 2011") Download | |
| Mar 19, 2019 | 1025 | U.S. Patent No. 6,664,195 ("Jang") Download | |
| Mar 19, 2019 | 1041 | Certified English translation of WO International Patent Pub. No. 2008/114341 ("Okuno PCT") Download |
