Case number IPR2020-01735
Semiconductor Components Industries, LLC doing business as ON Semiconductor et al. v. Invensas Corporation et al. > Documents
| Date Field | Doc. No. | Party | Description |
|---|---|---|---|
| Sep 1, 2021 | 11 | board | Final Written Decision: original Download |
| Dec 28, 2020 | 10 | board | Download |
| Dec 17, 2020 | 9 | board | Decision - Granting Institution of Inter Partes Review; Granting Motion for Joinder Download |
| Dec 4, 2020 | 8 | patent_own | Patent Owner Non-Opposition to Joinder Motion Download |
| Oct 21, 2020 | 7 | patent_own | Patent Owner Power of Attorney Download |
| Oct 21, 2020 | 6 | patent_own | Patent Owner Mandatory Notices Download |
| Oct 8, 2020 | 5 | board | Notice of Accord Filing Date Download |
| Sep 30, 2020 | 1007 | petitioner | "CMP Applications for Sub-0.25um Process Technologies" by D. Pramanik et al., Proceedings of the Second International Symposium on Chemical Mechanical Planarization in Integrated Circuit Device Manufacturing ("Pramanik1998") Download |
| Sep 30, 2020 | 1008 | petitioner | U.S. Patent No. 5,879,222 Download |
| Sep 30, 2020 | 1009 | petitioner | "Introduction to VLSI Systems" by C. Mead and L. Conway, Part 2 Download |
| Sep 30, 2020 | 1009 | petitioner | "Introduction to VLSI Systems" by C. Mead and L. Conway, Part 4 Download |
| Sep 30, 2020 | 1009 | petitioner | "Introduction to VLSI Systems" by C. Mead and L. Conway, Part 1 Download |
| Sep 30, 2020 | 1009 | petitioner | "Introduction to VLSI Systems" by C. Mead and L. Conway, Part 3 Download |
| Sep 30, 2020 | 1010 | petitioner | "Digital Integrated Circuits" by J. Rabaey, Part 4 Download |
| Sep 30, 2020 | 1010 | petitioner | "Digital Integrated Circuits" by J. Rabaey, Part 2 Download |
| Sep 30, 2020 | 1010 | petitioner | "Digital Integrated Circuits" by J. Rabaey, Part 3 Download |
| Sep 30, 2020 | 1010 | petitioner | "Digital Integrated Circuits" by J. Rabaey, Part 1 Download |
| Sep 30, 2020 | 1011 | petitioner | "Chemical Mechanical Planarization of Microelectronic Materials" by J. Steigerwald et al. Download |
| Sep 30, 2020 | 1012 | petitioner | "Principles of CMOS VLSI Design 2nd Edition" by N. Weste and K. Eshraghian, Part 4 Download |
| Sep 30, 2020 | 1012 | petitioner | "Principles of CMOS VLSI Design 2nd Edition" by N. Weste and K. Eshraghian, Part 2 Download |
| Sep 30, 2020 | 1012 | petitioner | "Principles of CMOS VLSI Design 2nd Edition" by N. Weste and K. Eshraghian, Part 1 Download |
| Sep 30, 2020 | 1012 | petitioner | "Principles of CMOS VLSI Design 2nd Edition" by N. Weste and K. Eshraghian, Part 3 Download |
| Sep 30, 2020 | 1013 | petitioner | "Implementation of CMP-based design rules and pattern practices" by L. E. Camilletti, Proc. IEEE/SEMI Adv. Semiconduct. Manufact. Conf., October 1995, pp. 2-4 Download |
| Sep 30, 2020 | 1014 | petitioner | "The role of dummy fill patterning practices on intra-die ILD thickness variation in CMP processes" by B. Stine et al., Proc. VLSI Multilevel Interconnect Conf., June 1996, pp. 421-423 Download |
| Sep 30, 2020 | 1015 | petitioner | "Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing," by H. Landis et al., Thin Solid Films (1992) 1-7 Download |
| Sep 30, 2020 | 1 | petitioner | PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,849,946 Download |
| Sep 30, 2020 | 1017 | petitioner | U.S. Patent No. 5,948,573 Download |
| Sep 30, 2020 | 1018 | petitioner | U.S. Patent No. 5,639,679 Download |
| Sep 30, 2020 | 1019 | petitioner | U.S. Patent No. 5,928,959 Download |
| Sep 30, 2020 | 1020 | petitioner | U.S. Patent No. 5,721,172 Download |
| Sep 30, 2020 | 1021 | petitioner | U.S. Patent No. 5,943,590 Download |
| Sep 30, 2020 | 1022 | petitioner | U.S. Patent No. 5,602,423 Download |
| Sep 30, 2020 | 1023 | petitioner | U.S. Patent No. 5,652,465 Download |
| Sep 30, 2020 | 1024 | petitioner | U.S. Patent No. 6,103,626 Download |
| Sep 30, 2020 | 1025 | petitioner | U.S. Patent No. 5,923,563 Download |
| Sep 30, 2020 | 1026 | petitioner | U.S. Patent No. 6,109,775 Download |
| Sep 30, 2020 | 1027 | petitioner | Email from Duane Boning dated March 10, 1998 Download |
| Sep 30, 2020 | 1028 | petitioner | Claim Construction Order (Nov. 16, 2018) from Case 1:17-cv-01363-MN (D. Del.) Download |
| Sep 30, 2020 | 1029 | petitioner | Claim Construction Order (Oct. 26, 2018) from Case 2:17-CV-00670-RWS-RSP (E.D. Tx.) Download |
| Sep 30, 2020 | 1030 | petitioner | IPR2017-00107 Decision Denying Institution of Inter Partes Review (Paper 7) Download |
| Sep 30, 2020 | 1031 | petitioner | IPR2018-01402 Petition for Inter Partes Review of U.S. Patent No. 6,849,946 Download |
| Sep 30, 2020 | 1032 | petitioner | IPR2018-01402 Decision to Terminate Proceeding (Paper 11) Download |
| Sep 30, 2020 | 3 | petitioner | Motion for Joinder Download |
| Sep 30, 2020 | 4 | petitioner | Power of Attorney Download |
| Sep 30, 2020 | 1006 | petitioner | "Integration of CMP Into Deep Sub-micron Multilevel Metallization Circuits" by D. Pramanik et al., Proceedings of the First International Symposium on Chemical Mechanical Planarization in Integrated Circuit Device Manufacturing ("Pramanik1997") Download |
| Sep 30, 2020 | 1005 | petitioner | "The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes," by B. Stine et al., IEEE Trans. On Elec. Devices, Vol. 45 No. 3 March 1998, pp. 665-679 ("Stine1998") Download |
| Sep 30, 2020 | 1004 | petitioner | U.S. Patent No. 6,093,631 Download |
| Sep 30, 2020 | 1003 | petitioner | Prosecution History for U.S. Patent No. 6,849,946 Download |
| Sep 30, 2020 | 1002 | petitioner | Declaration of Dr. Duane S. Boning Download |
| Sep 30, 2020 | 1001 | petitioner | U.S. Patent No. 6,849,946 Download |
| Sep 30, 2020 | 1016 | petitioner | "Multilevel interconnect system for 0.35-um CMOS LSI's with metal dummy planarization process and thin tungsten wirings," by Ichikawa et al., VLSI Multilevel Interconnect Conf., June 1995, pp. 254-260 Download |
