Search
Patexia Research
Case number 3:11-cv-01403

Steren Electronics International, LLC v. Perfect 10 Antenna Company et al > Summary

Court Case Number 3:11-cv-01403

Filing Date Jun 24, 2011

Termination Date Nov 3, 2011

Court California Southern District Court

Status Dismissed - Settled

Plaintiff

Steren Electronics International Llc

Defendant

2

Perfect 10 Antenna

Ciena Corporation

Cause

35:0271 Patent Infringement

Related Patents

Doc No Title Issue date
07227918 Clock data recovery circuitry associated with programmable logic device circuitry Jun 5, 2007
07091613 Elongated bonding pad for wire bonding and sort probing Aug 15, 2006
06985021 Circuits and techniques for conditioning differential signals Jan 10, 2006
06859064 Techniques for reducing leakage current in on-chip impedance termination circuits Feb 22, 2005
06856180 Programmable loop bandwidth in phase locked loop (PLL) circuit Feb 15, 2005
06798302 Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system Sep 28, 2004
06640333 Architecture for a sea of platforms Oct 28, 2003
06564361 Method and apparatus for timing driven resynthesis May 13, 2003
06459313 IO power management: synchronously regulated output skew Oct 1, 2002
06342794 Interface for low-voltage semiconductor devices Jan 29, 2002
06313683 Method of providing clock signals to load circuits in an ASIC device Nov 6, 2001
06157215 Method and apparatus for controlling impedance Dec 5, 2000
06118177 Heatspreader for a flip chip device, and method for connecting the heatspreader Sep 12, 2000
06028467 Differential output circuit Feb 22, 2000
05952726 Flip chip bump distribution on die Sep 14, 1999
05834849 High density integrated circuit pad structures Nov 10, 1998
05822553 Multiple parallel digital data stream channel controller architecture Oct 13, 1998
05801958 Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information Sep 1, 1998
05784649 Multi-threaded FIFO pool buffer and bus transfer control system Jul 21, 1998
05752032 Adaptive device driver using controller hardware sub-element identifier May 12, 1998
05731711 Integrated circuit chip with adaptive input-output port Mar 24, 1998
05526277 ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof Jun 11, 1996
05222030 Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof Jun 22, 1993
Menu