Systems and methods for hard error reduction in a solid state memory device | Patent Number 09576683
US 09576683 B2Filled DateFeb 11, 2014
Priority DateFeb 6, 2014
Publication DateAug 6, 2015
Expiration DateFeb 5, 2034
Inventor/ApplicantsYunxiang Wu
Yu Cai
Erich F. Haratsch
Yu Cai
Erich F. Haratsch
ExaminesTABONE JR, JOHN J
Art Unit2117
Technology Center2100
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