Loop optimization in a circuit design netlist | Patent Number 10878150

US 10878150 B1
Application Number16573233
Publication Number-
Pendency1 year, 3 months, 14 days
Filled DateSep 17, 2019
Priority DateSep 17, 2019
Publication Date-
Expiration DateSep 16, 2039
Inventor/ApplicantsHossein Omidian Savarbaghi
ExaminesLEVIN, NAUM B
Art Unit2851
Technology Center2800
Assignments
Xilinx
Current
XilinxAdvanced Micro Devices Inc
Original
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