Placement of logic based on relative activation rates | Patent Number 11651127

US 11651127 B2
Application Number17399523
Publication NumberUS 20230050757 A1
Pendency1 year, 9 months, 8 days
Filled DateAug 11, 2021
Priority DateAug 11, 2021
Publication DateFeb 16, 2023
Expiration DateAug 10, 2041
Inventor/ApplicantsStephen Andrew Neuendorffer
Jianyi Cheng
ExaminesLIN, ARIC
Art Unit2851
Technology Center2800
Assignments
Xilinx
Current
XilinxAdvanced Micro Devices Inc
Original
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