Compaction of multiplier and adder circuits | Patent Number 11768663

US 11768663 B1
Application Number17014410
Publication Number-
Pendency3 years, 18 days
Filled DateSep 8, 2020
Priority DateSep 8, 2020
Publication Date-
Expiration DateSep 7, 2040
Inventor/ApplicantsAman Gayasen
Srijan Tiwary
ExaminesSANDIFER, MATTHEW D
Art Unit2182
Technology Center2100
Assignments
Xilinx
Current
XilinxAdvanced Micro Devices Inc
Original
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