Power semiconductor device and substrate with dimple region | Patent Number 11842968
US 11842968 B2Filled DateApr 29, 2022
Priority DateOct 25, 2018
Publication DateAug 11, 2022
Expiration DateOct 24, 2038
Inventor/ApplicantsYuya Muramatsu
Atsuki FUJITA
Noriyuki Besshi
Hiroaki Haruna
Atsuki Fujita
Noriyuki BESSHI
Yutaro SUGI
Kohei Yabuta
Takayuki Yamada
Hiroaki HARUNA
Yutaro Sugi
Masaru FUKU
Kohei YABUTA
Masaru Fuku
Takayuki YAMADA
Yuya MURAMATSU
Atsuki FUJITA
Noriyuki Besshi
Hiroaki Haruna
Atsuki Fujita
Noriyuki BESSHI
Yutaro SUGI
Kohei Yabuta
Takayuki Yamada
Hiroaki HARUNA
Yutaro Sugi
Masaru FUKU
Kohei YABUTA
Masaru Fuku
Takayuki YAMADA
Yuya MURAMATSU
ExaminesGEYER, SCOTT B
Art Unit2812
Technology Center2800
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