Wafer level stacked structures having integrated passive features | Patent Number 11854958

US 11854958 B2
Application Number17875205
Publication NumberUS 20220367339 A1
Pendency1 year, 5 months, 2 days
Filled DateJul 27, 2022
Priority DateOct 28, 2019
Publication DateNov 17, 2022
Expiration DateOct 27, 2039
Inventor/ApplicantsMarco Francesco Aimi
Joleyn Eileen Brewer
Joseph Alfred Iannotti
ExaminesKIELIN, ERIK J
Art Unit2814
Technology Center2800
Assignments
General Electric
Current
General Electric
Original
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