Scan architecture for interconnect testing in 3D integrated circuits | Patent Number 11899064

US 11899064 B2
Application Number18080680
Publication NumberUS 20230113905 A1
Pendency1 year, 2 months, 2 days
Filled DateDec 13, 2022
Priority DateJun 2, 2016
Publication DateApr 13, 2023
Expiration DateJun 1, 2036
Inventor/ApplicantsSaman M.I. ADHAM
Marat GERSHOIG
Sandeep Kumar GOEL
Saman M. I. Adham
Yun-Han LEE
Sandeep Kumar Goel
Marat Gershoig
Yun-Han Lee
ExaminesTANG, RONG
Art Unit2111
Technology Center2100
Assignments
Taiwan Semiconductor Manufacturing Company
Current
Taiwan Semiconductor Manufacturing Company
Original
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