Apparatus and method to manage energy usage of a processor | Patent Publication Number 20140189405
US 20140189405 A1Shaun M. Conrad
SHAUN M. CONRAD
Stephen H. Gunther
In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor and a voltage regulator coupled to the processor, during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode, and to control the voltage regulator based at least in part on the predicted energy usage. Other embodiments are described and claimed.
- 1. A processor comprising:nat least one processor core; anda power controller having energy usage logic to predict an energy usage of the processor during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode and to control the voltage regulator based at least in part on the predicted energy usage.
- 9. A system comprising:na voltage regulator;a processor having at least one processor core and energy usage logic to predict energy usage of the processor and the voltage regulator during a low power period according to a first plan and a second plan, wherein the voltage regulator is in an active state throughout the low power period according to the first plan, and the voltage regulator is inactive during at least a first portion of the low power period according to the second plan, and select one of the first and second plans based on a comparison of the energy usage according to the first and second plans; anda dynamic random access memory (DRAM) coupled to the processor to store.
- 14. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:npredicting first energy usage of a system that includes a processor and a voltage regulator during a low power period according to a first plan in which the voltage regulator is in an active state throughout the low power period;predicting, based on voltage versus time decay data, second energy usage by the system during the low power period according to a second plan wherein the voltage regulator is deactivated during at least a first time portion of the low power period; andselecting one of the first plan and the second plan based on a comparison of the first energy usage with the second energy usage.
This application is a continuation of U.S. patent application Ser. No. 13/729,908, filed Dec. 28, 2012, the content of which is hereby incorporated by reference.
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy usage. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooksâ„¢, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
To save energy during periods of low activity, a processor may be placed in an idle power state, e.g., one of states C1 to CN that consumes less power than when the processor is in an active state, according to the Advanced Configuration and Power Interface (ACPI) standard, e.g., Rev. 5.0, published November, 2011.
In various embodiments, a processor may be placed from an active state, e.g., C0, into an idle power state, e.g., a low power state such as one of the C1-CN states. Placement of the processor in the idle power state typically includes reduction of voltage of a system that includes the processor and decoupling capacitors. The voltage reduction may be actively managed by a voltage regulator controller that controls a voltage regulator (VR), which typically is external to the processor. The voltage reduction may also be accomplished by passive reduction of the voltage, e.g., through bleed-off of stored charge in the processor and the capacitors. In some situations, passive reduction of the processor voltage to a steady-state idle voltage, e.g., shutoff (or reduction in operating voltage) of the voltage regulator and/or reduction in operation capacity of other processor circuitry during voltage reduction period can result in a reduction of energy cost.
However, when the processor is to be reinstated to the active state the voltage regulator and/or processor circuitry may need to be activated. For example, the VR can have an associated energy cost of VR reactivation. In some circumstances, the energy cost saved by shutoff (or reduced operating voltage) of the VR (or reduction of circuitry operation capacity) during voltage reduction is outweighed by the energy cost of VR reactivation/circuitry reinstatement. In various embodiments, energy cost prediction logic within the processor can predict a first energy cost associated with a first power modification plan that includes passive voltage reduction, maintenance of the processor voltage during the idle power state (e.g. low power state C3), and voltage reinstatement (which may include VR activation or reinstatement from a reduced operating voltage to a full operating voltage, and/or processor circuit reactivation to full operation). The energy cost prediction logic may compare the first predicted energy cost to a second predicted energy cost associated with a second power modification plan that includes active voltage reduction, maintenance of the processor voltage during the idle power state, and voltage reinstatement (without energy costs, e.g., to reactivate the VR or processor circuitry). Based at least in part on this comparison, the energy cost prediction logic can select the power modification plan that has a smaller associated energy cost. Modification of the processor power level, e.g., voltage reduction to idle voltage, maintenance of idle voltage during an idle period, and voltage reinstatement can be executed according to the selected power modification plan.
Although the scope of the present invention is not limited in this regard, deep low power state re-entry control as described herein can be implemented via firmware, hardware, software, and combinations thereof, e.g., via voltage control logic that may be external to, or internal to the processor.
Referring now to
As seen, processor 110 may be a single die processor including multiple cores 120a-120n. In addition, each core may be associated with an individual voltage regulator 125a-125n. Accordingly, an integrated voltage regulator (IVR) implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core.
Still referring to
Also shown is a power control unit (PCU) 138, which may include hardware, software and/or firmware to perform power management operations with regard to processor 110. In various embodiments, PCU 138 may include logic to perform operations with regard to package low power state entry and re-entry in accordance with an embodiment of the present invention. Furthermore, PCU 138 may be coupled via a dedicated interface to external voltage regulator 160, which includes a voltage regulator controller 162. In this way, PCU 138 can instruct the voltage regulator 160 (e.g., via voltage regulator controller 162) to provide a requested regulated voltage to the processor 110. In an embodiment, the VR controller 162 may be a microcontroller such as an 8051-based controller or other such controller configured to execute programmable instructions.
While not shown for ease of illustration, understand that additional components may be present within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of
Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems, and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.
Note that the power control associated with one or more voltage regulators described herein may be independent of and complementary to an operating system (OS)-based mechanism, such as the ACPI standard. With regard to power states, ACPI specifies different power usage states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states).
When all cores of a multicore processor are in a core low power state, the processor can be placed in a package low power state, such as a package C6 low power state which is a deep low power state in which certain clock generation circuitry including phase locked loops (PLLs) are turned off (e.g., PLLs in an uncore portion), internal voltages of uncore rails are reduced and core caches and core state are flushed to a shared cache memory, e.g., a last level cache.
Energy usage logic 130 within the PCU 138 may predict an energy cost associated with each of a plurality of power modification plans. For example, a power modification plan can include information associated with a reduction of the processor voltage from an active power state to an idle power state (e.g., C3, or C6), maintenance of the processor in the idle power state for a processor idle time period, and reinstatement of the processor to an active state, and each power modification plan can be accomplished according to a distinct voltage modification plan that specifies target voltages and associated time periods for each target voltage. In some embodiments, each power modification plan is stored in a table of power modification plans, and each power modification plan may be associated with a corresponding processor application.
The prediction of the energy cost of the voltage reduction phase of a power modification plan may be based on data received from the VR controller 162 or stored in another location, e.g., voltage v. time for a previous voltage reduction, e.g., a length of time for the processor voltage to reach an idle voltage Vidle beginning at an active voltage Vactive in a previous power modification. For example, data may be recorded and stored for a most recent power modification (associated with a program application) including voltage reduction to a processor idle state, maintenance of the processor at the processor idle power for an idle time period, and reinstatement of the processor to an active processor state. The usage logic 130 can select a power modification plan that has a smaller associated energy cost than the other power modification plans, and can direct the voltage regulator controller 162 to conduct the power modification (e.g., voltage reduction from active voltage to idle voltage, maintenance at idle voltage for a specified idle time period, and reinstatement of the processor to active voltage) according to the selected power modification plan. Various power modification plans to accomplish power modification can be compared. For instance, one power modification may include active voltage regulation by the external VR 160 throughout a voltage modification time period, e.g., from beginning of processor voltage reduction through reinstatement of active processor voltage. Another power modification plan may include passive reduction in voltage during a portion of the voltage modification period. Other power modification plans may include other approaches to conserve energy during portions of voltage modification, e.g., shutoff of various processor circuitry (e.g., clock circuits) during portions of the voltage modification period.
The energy usage logic 130 may calculate predicted energy cost associated with each of the several power modification plans. For example, the energy usage logic 130 may calculate a first energy cost associated with a first power modification plan that includes a first energy cost first portion due to passive voltage reduction to the idle voltage, e.g., shutoff of the external VR 160 while the processor voltage is permitted to decay until it reaches the intended idle voltage of a selected low power state (e.g., C3 or C6). A second portion of the first energy cost may include energy expended during the idle power state (also “idle phase†), e.g., energy expended by the processor 110 at a low voltage (idle) state, and may also include a “wake-up†energy cost to reinstate the external VR 160 after it has been shut off (e.g., the VR 160 to regulate the processor voltage during the idle phase). A third portion of the first energy cost may include energy expended to reinstate the processor to the active state, including energy supplied to the processor 110 and energy expended by the external VR 160 during reinstatement.
Further, the energy usage logic 130 may calculate a second energy cost associated with a second power modification plan that includes an active control of the processor voltage by the external VR 160. A first portion of the second energy cost may include energy expended in actively reducing the processor voltage, e.g., by the external VR 160. A second portion of the second energy cost may include energy expended during the idle power state and may include energy expended by the external VR 160 to supply an idle power state voltage. A third portion of the second energy cost may include energy expended during the reinstatement of the processor to the active state and may include energy expended by the external VR 160 during the reinstatement of the processor to the active state. The energy usage logic may add up the first, second, and third portions of the second energy cost to arrive at the second energy cost.
The energy usage logic 130 may perform a comparison of the first energy cost to the second energy cost and may select the power management plan with the smaller energy cost. The VR controller 162 may perform the power modification according to the selected power modification plan.
In an example, the processor is to become idle, e.g., enter the C6 state in which the processor voltage is to go to zero volts. The energy usage logic may determine, from a history of processor usage in a similar programming environment, e.g., stored in storage (e.g., DRAM) and retrievable upon request by the energy usage logic, and a current programming environment, that the processor has a high likelihood of reduction of the processor voltage to zero volts before the processor is to be reinstated to the active state, e.g., C0. The energy usage logic 130 may calculate a first modification plan energy usage associated with passive voltage decay of the processor to zero volts, passive maintenance at zero volts, and subsequent reactivation of the processor. Because the target voltage is zero volts, there is no need to actively regulate the processor voltage during the voltage decay (as might be needed if the target voltage were a non-zero value), and hence there will be energy saved in shutdown of the VR 160 during the decay phase and the idle phase. There may be a reactivation energy cost associated with reactivation of the VR 160. The energy usage logic 130 may determine the first modification plan energy usage as the sum of the energy usage associated with each of the passive decay phase, idle phase, and reinstatement phase.
The energy usage logic may determine a second energy usage in which the voltage regulator remains active throughout the voltage reduction phase, idle phase, and reinstatement phase. By maintenance of the VR in the active state throughout the voltage reduction to reinstatement period, there is no cost associated with reactivation of the VR 160. However, there would be an energy cost associated with maintenance of the VR in the active state throughout the power modification. (In other embodiments, the VR may be operated at one or more reduced levels during some portions of the voltage reduction to reinstatement period, with an associated energy cost).
The energy usage logic 130 may compare the first energy usage to the second energy usage, and may select one of the first and second power modification plans based comparison of associated energy usage, e.g., the power modification plan that has the smaller energy usage. The energy usage logic 130 may then direct the VR controller 162 to execute the selected power modification plan.
The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100.
Referring now to
Based on the voltage decay time period and a predicted length of time that the processor is expected to be in the idle power state, the energy usage logic can predict first energy usage for a first power modification plan that includes passive voltage decay, which can be compared with a prediction of second energy usage of the processor for a second power modification plan that includes, e.g., active control of the voltage decay phase and idle phase by a voltage regulator coupled to the processor, or active use of the processor circuit, or active use of another circuit that consumes energy. The energy usage logic may determine which power modification plan to invoke based on the energy usage comparison.
Referring now to
Based on initial voltage versus time data received from, e.g., a voltage regulator controller, energy usage logic within a processor may predict a time Tidle at which the processor arrives at the idle processor voltage Vidle, and the energy usage logic may predict based, e.g., on processor history, a time period (ΔT=Treinstate−Tidle) during which the processor is in the idle power state. The energy usage logic may determine a first energy cost associated with a first power modification plan for the decay phase, the idle phase, and the reinstatement phase with passive voltage decay, e.g., voltage regulator shut off during voltage decay, the first energy cost determined based on Tidle, ΔT, energy to reactivate the voltage regulator, and other information. The energy usage logic may also determine a second energy cost associated with a second power modification plan in which the voltage regulator is actively regulating processor voltage throughout the decay phase, the idle phase, and the reinstatement phase. The energy usage logic may select one of the first modification plan and the second modification plan based on a comparison of corresponding energy usage.
Referring now to
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to
With further reference to
While shown with this particular implementation in the embodiment of
Referring now to
In general, each core 610 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 6400-640n. In various embodiments, LLC 640 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 630 thus couples the cores together, and provides interconnection between the cores, graphics domain 620 and system agent circuitry 650. In one embodiment, interconnect 630 can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain.
As further seen, system agent domain 650 may include display controller 652 which may provide control of and an interface to an associated display. As further seen, system agent domain 650 may include a power control unit 655 which can include energy usage logic 659 in accordance with an embodiment of the present invention.
As further seen in
Embodiments may be implemented in many different system types. Referring now to
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Furthermore, chipset 790 includes an interface 792 to couple chipset 790 with a high performance graphics engine 738, by a P-P interconnect 739. In turn, chipset 790 may be coupled to a first bus 716 via an interface 796. As shown in
Referring now to
As seen in
Processor 810 may include central processing unit (CPU) 811 that includes a plurality of cores 812a-812n. Each core may have a corresponding integrated voltage regulator 814a-814n. The CPU 811 may also include power control unit (PCU) 816 that includes power control logic 818 to predict energy cost of various power modification plans and to select one of the power modification plans based at least on energy considerations, as in embodiments of the present invention.
Processor 810 may communicate with a system memory 815, which in an embodiment can be implemented via multiple memory devices to provide for a given amount of system memory. To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage 820 may also couple to processor 810. Also shown in
Various input/output (IO) devices may be present within system 800. Specifically shown in the embodiment of
For perceptual computing and other purposes, various sensors may be present within the system and can be coupled to processor 810 in different manners. Certain inertial and environmental sensors may couple to processor 810 through a sensor hub 840, e.g., via an I2C interconnect. In the embodiment shown in
Also seen in
System 800 can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in
As further seen in
In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit 856 which in turn may couple to a subscriber identity module (SIM) 857. In addition, to enable receipt and use of location information, a GPS module 855 may also be present. Note that in the embodiment shown in
To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) 860, which may couple to processor 810 via a high definition audio (HDA) link. Similarly, DSP 860 may communicate with an integrated coder/decoder (CODEC) and amplifier 862 that in turn may couple to output speakers 863 which may be implemented within the chassis. Similarly, amplifier and CODEC 862 can be coupled to receive audio inputs from a microphone 865 which in an embodiment can be implemented via dual array microphones to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC 862 to a headphone jack 864. Although shown with these particular components in the embodiment of
Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.