Method and Apparatus for Evaluating the Timing Effects of Logic Block Location Changes in Integrated Circuit Design | Patent Publication Number 20090064068

US 20090064068 A1
Patent Number-
Application Number11848421
Filled DateAug 31, 2007
Priority DateAug 31, 2007
Publication DateMar 5, 2009
Original AssigneeInternational Business Machines
Current AssigneeToshiba America Electronic Components
Inventor/ApplicantsAlvan Wing Ng
Taku Uchino
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