MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES | Patent Publication Number 20150138864
US 20150138864 A1Lsi Broadcom
Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.
- 1. A memory cell array comprising:nfirst and second segments with corresponding local bitlines connected to one or more memory cells; andfirst and a second metallization layers, the second metallization layer including first and second global bitlines, and the first metallization layer including local bitlines;wherein, in each of the first segments, local bitlines are connected to one of the first global bitlines;wherein, in each of the second segments, local bitlines are connected to one of the second global bitlines; andwherein the first and the second global bitlines extend in a direction that is across the first and the second segments.
- 9. A memory device, comprising:na memory module, comprising:a second metallization layer comprising first and second pairs of global bitlines; anda first metallization layer comprising first and second segments of memory cells,wherein, each segment of memory cells comprises a pair of local bitlines coupled to the memory cells,wherein, the pair of local bitlines of the first segment is coupled to the first pair of global bitlines, andwherein, the pair of local bitlines of the second segment is coupled to the second pair of global bitlines, andwherein, the global bitlines extend in a direction that is across the first and the second segments.
This patent application claims priority to, and thus the benefit of an earlier filing date from, U.S. Provisional Patent Application No. 61/904,739 (filed Nov. 15, 2013), the entire contents of which are hereby incorporated by reference.
The invention generally relates to memory systems, and in particular to a low-power, high-density, and high-speed memory architecture.
Memory devices typically include a memory cell array with a grid of columns and rows. For semiconductor memory architectures such as Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), rows and columns are referred to as wordlines and bitlines, respectively. Memory cells within the array store bits and are disposed at intersections of wordlines and bitlines. Address decoders select the appropriate row and column to perform a read or write operation on the desired memory cell. A memory architecture with a high density means that the memory cell array contains many rows and columns. Since the bitlines run through the entire range of rows, an increase in the number of rows increases the total capacitance of the bitlines, which not only degrades performance but also increases dynamic power consumption. In a previous solution, the memory array is divided into a number of banks comprising a limited number of rows and a local input/output (I/O) circuit specific to each bank. Unfortunately, the local I/O circuits for each bank increase the area overhead of the memory device.
Systems and methods presented herein provide a memory cell array configuration that operates at low power and high speed without an increase in area overhead. In one embodiment, a memory cell array is disclosed. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The first metallization layer includes local bitlines. The second metallization layer includes first and second global bitlines. In each of the first segments, local bitlines are connected to the first global bitlines and in each of the second segments, local bitlines are connected to the second global bitlines.
The various embodiments disclosed herein may be implemented in a variety of ways as a matter of design choice. For example, some embodiments herein are implemented in hardware whereas other embodiments may include processes that are operable to construct and/or operate the hardware. Other exemplary embodiments are described below.
Some embodiments of the present invention are now described, by way of example only, and with reference to the accompanying drawings. The same reference number represents the same element or the same type of element on all drawings.
The figures and the following description illustrate specific exemplary embodiments of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within the scope of the invention. Furthermore, any examples described herein are intended to aid in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited examples and conditions. As a result, the invention is not limited to the specific embodiments or examples described below.
The memory array architecture 100 of
The memory array architecture 100 includes two metallization layers. When thought of as x, y, and z orthogonal planes, the two metallization layers of the memory array architecture 100 each cover separate horizontal planes in the x and y directions and are spaced over each other in the z direction. Bitlines and their complements run parallel with one another in the y direction in a horizontal plane, and the wordlines run in the x direction of the horizontal plane. Thus, the two metallization layers may be referred to as an upper metallization layer and lower metallization layer.
The memory array architecture 100 is divided into a number of segments 110/111, of which there are two types—even segments 110 and odd segments 111. The even segments 110 and the odd segments 111 may alternate one after another throughout the memory architecture 100 in the y direction, as shown in
Each segment 110/111 is associated with a local bitline 120 that is specific to that segment. The local bitline 120 runs in lower metallization, as indicated by the dashed line in
In the upper metallization layer, there are two global bitlines—an even global bitline 140 and an odd global bitline 130. Again, it is generally understood that a global bitline can comprise a pair. Thus, the even global bitline 140 may be referred to as a true even global bitline 140-1 and a complementary even global bitline 140-2. Similarly, the odd global bitline 130 may be referred to as a true odd global bitline 130-1 and a complementary odd global bitline 130-2. For a given column, there are the two global bitlines 130/140 running in upper metallization. Thus, each column in the memory array architecture 100 has a plurality of bitline pairs—two pairs of global bitlines in upper metallization (e.g., 130-1, 130-2, 140-1, and 140-2) running across (or above) a range of segments 110/111, and a pair of local bitlines in lower metallization specific to each segment 110/111 (e.g., 120-1 and 120-2).
The local bitline 120 connects to either the even global bitline 140 or the odd global bitline 130 depending on the segment 110/111 in which the local bitline 120 is located. A global I/O toggles one of the two global bitlines 130/140 (i.e., even or odd global bitline) depending on the segment that is being selected (i.e., even or odd segment). To illustrate, in segment 110-1 (i.e., the first even segment), the local bitline 120 connects to the even global bitline 140. In segment 111-1 (i.e., the first odd segment), the local bitline 120 connects to the odd global bitline 130. In order to perform a read or write operation on, for example, a memory cell in the first even segment (i.e., 110-1), a global I/O toggles the even global bitline (i.e., 140) in the column m of that memory cell.
When there are bitline pairs in the memory array architecture 100, the true and complement of a local bitline (i.e., 120-1, 120-2) in an even segment (e.g., 110-1, 110-2, or 110-3) connect to the true and complement, respectively, of the even global bitline (i.e., 140-1, 140-2). And, the true and complement of a local bitline (i.e., 120-1, 120-2) in an odd segment (e.g., 111-1, 111-2, 111-3) connect to the true and complement, respectively, of the odd global bitline (i.e., 130-1, 130-2). This structure may be repeated for each of the m columns of the memory array architecture 100 as shown in
As seen in
It will be appreciated that the terms upper, lower, first, second, even, and odd and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular orientation or order. In other words, the terms so used are interchangeable under appropriate circumstances and the embodiments of the disclosure herein can operate in orientations and sequences other than that which is described or illustrated herein. Furthermore, while the memory array architecture 100 has been described above with reference to SRAM, embodiments described herein may be useful for other high density memories such as DRAM and other memory architectures. Additionally, the metallization layers may comprise any conductive material such as metal or polysilicon.
In some embodiments, the physical implementation of the memory array architecture 100 can differ from that which is described or illustrated. For example, bitlines and wordlines need not necessarily be orthogonal to one another as shown in