Block level design method for heterogeneous PG-structure cells | Patent Publication Number 20230153507

US 20230153507 A1

Patent NumberUS 11853678 B2

Application Number18096906

Filled DateJan 13, 2023

Priority DateDec 15, 2016

Publication DateMay 18, 2023

Original AssigneeTaiwan Semiconductor Manufacturing Company

Current AssigneeTaiwan Semiconductor Manufacturing Company

Inventor/ApplicantsYen-Hung Lin
Yuan-Te Hou
Chung-Hsing Wang

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