David Ruben Pedersen
Examiner (ID: 2573)
Most Active Art Unit | 3667 |
Art Unit(s) | 3667 |
Total Applications | 88 |
Issued Applications | 4 |
Pending Applications | 71 |
Abandoned Applications | 13 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 975225
[patent_doc_number] => 06933033
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-08-23
[patent_title] => 'Scribed interleaf separator wafer packaging'
[patent_app_type] => utility
[patent_app_number] => 10/919640
[patent_app_country] => US
[patent_app_date] => 2004-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 608
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/933/06933033.pdf
[firstpage_image] =>[orig_patent_app_number] => 10919640
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/919640 | Scribed interleaf separator wafer packaging | Aug 16, 2004 | Issued |
Array
(
[id] => 979376
[patent_doc_number] => 06930382
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/875190
[patent_app_country] => US
[patent_app_date] => 2004-06-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/930/06930382.pdf
[firstpage_image] =>[orig_patent_app_number] => 10875190
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/875190 | Semiconductor device and method of manufacturing the same | Jun 24, 2004 | Issued |
Array
(
[id] => 788138
[patent_doc_number] => 06987070
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-17
[patent_title] => 'Method for forming low-k dielectric layer of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/874928
[patent_app_country] => US
[patent_app_date] => 2004-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/987/06987070.pdf
[firstpage_image] =>[orig_patent_app_number] => 10874928
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/874928 | Method for forming low-k dielectric layer of semiconductor device | Jun 22, 2004 | Issued |
Array
(
[id] => 1047316
[patent_doc_number] => 06864540
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-08
[patent_title] => 'High performance FET with elevated source/drain region'
[patent_app_type] => utility
[patent_app_number] => 10/851530
[patent_app_country] => US
[patent_app_date] => 2004-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 2763
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[pdf_file] => patents/06/864/06864540.pdf
[firstpage_image] =>[orig_patent_app_number] => 10851530
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/851530 | High performance FET with elevated source/drain region | May 20, 2004 | Issued |
Array
(
[id] => 1034479
[patent_doc_number] => 06875688
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-05
[patent_title] => 'Method for reactive ion etch processing of a dual damascene structure'
[patent_app_type] => utility
[patent_app_number] => 10/709630
[patent_app_country] => US
[patent_app_date] => 2004-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/875/06875688.pdf
[firstpage_image] =>[orig_patent_app_number] => 10709630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709630 | Method for reactive ion etch processing of a dual damascene structure | May 17, 2004 | Issued |
Array
(
[id] => 946570
[patent_doc_number] => 06964902
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'Method for removing nanoclusters from selected regions'
[patent_app_type] => utility
[patent_app_number] => 10/787510
[patent_app_country] => US
[patent_app_date] => 2004-02-26
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[pdf_file] => patents/06/964/06964902.pdf
[firstpage_image] =>[orig_patent_app_number] => 10787510
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/787510 | Method for removing nanoclusters from selected regions | Feb 25, 2004 | Issued |
Array
(
[id] => 7465544
[patent_doc_number] => 20040166656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 10/785103
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 9392
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[pdf_file] => publications/A1/0166/20040166656.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785103
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785103 | Method of fabricating semiconductor device | Feb 24, 2004 | Issued |
Array
(
[id] => 7413074
[patent_doc_number] => 20040228068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Capacitor and memory structure and method'
[patent_app_type] => new
[patent_app_number] => 10/785505
[patent_app_country] => US
[patent_app_date] => 2004-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 2493
[patent_no_of_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20040228068.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785505
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785505 | Capacitor and memory structure and method | Feb 23, 2004 | Abandoned |
Array
(
[id] => 7677535
[patent_doc_number] => 20040152291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Semiconductor devices and methods for fabricating the same'
[patent_app_type] => new
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[pdf_file] => publications/A1/0152/20040152291.pdf
[firstpage_image] =>[orig_patent_app_number] => 10757820
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/757820 | Semiconductor devices and methods for fabricating the same | Jan 14, 2004 | Issued |
Array
(
[id] => 6981135
[patent_doc_number] => 20050151203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Temporary self-aligned stop layer is applied on silicon sidewall'
[patent_app_type] => utility
[patent_app_number] => 10/754833
[patent_app_country] => US
[patent_app_date] => 2004-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0151/20050151203.pdf
[firstpage_image] =>[orig_patent_app_number] => 10754833
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/754833 | Temporary self-aligned stop layer is applied on silicon sidewall | Jan 8, 2004 | Issued |
Array
(
[id] => 956205
[patent_doc_number] => 06955955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'STI liner for SOI structure'
[patent_app_type] => utility
[patent_app_number] => 10/747494
[patent_app_country] => US
[patent_app_date] => 2003-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3766
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/955/06955955.pdf
[firstpage_image] =>[orig_patent_app_number] => 10747494
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/747494 | STI liner for SOI structure | Dec 28, 2003 | Issued |
Array
(
[id] => 7428922
[patent_doc_number] => 20040266032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor'
[patent_app_type] => new
[patent_app_number] => 10/741670
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0266/20040266032.pdf
[firstpage_image] =>[orig_patent_app_number] => 10741670
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/741670 | Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor | Dec 17, 2003 | Issued |
Array
(
[id] => 979496
[patent_doc_number] => 06930502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Method using conductive atomic force microscopy to measure contact leakage current'
[patent_app_type] => utility
[patent_app_number] => 10/734020
[patent_app_country] => US
[patent_app_date] => 2003-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/930/06930502.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734020
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734020 | Method using conductive atomic force microscopy to measure contact leakage current | Dec 9, 2003 | Issued |
Array
(
[id] => 7466652
[patent_doc_number] => 20040101984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-27
[patent_title] => 'Method for performing an alignment measurement of two patterns in different layers on a semiconductor wafer'
[patent_app_type] => new
[patent_app_number] => 10/713690
[patent_app_country] => US
[patent_app_date] => 2003-11-14
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[firstpage_image] =>[orig_patent_app_number] => 10713690
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/713690 | Method for performing an alignment measurement of two patterns in different layers on a semiconductor wafer | Nov 13, 2003 | Issued |
Array
(
[id] => 1040546
[patent_doc_number] => 06869844
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Method and structure for protecting NROM devices from induced charge damage during device fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/701780
[patent_app_country] => US
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[pdf_file] => patents/06/869/06869844.pdf
[firstpage_image] =>[orig_patent_app_number] => 10701780
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/701780 | Method and structure for protecting NROM devices from induced charge damage during device fabrication | Nov 4, 2003 | Issued |
Array
(
[id] => 7365286
[patent_doc_number] => 20040092101
[patent_country] => US
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[patent_issue_date] => 2004-05-13
[patent_title] => 'Cu film deposition equipment of semiconductor device'
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[patent_app_number] => 10/697320
[patent_app_country] => US
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[pdf_file] => publications/A1/0092/20040092101.pdf
[firstpage_image] =>[orig_patent_app_number] => 10697320
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697320 | Cu film deposition equipment of semiconductor device | Oct 30, 2003 | Issued |
Array
(
[id] => 963644
[patent_doc_number] => 06949456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'Method for manufacturing semiconductor device having porous structure with air-gaps'
[patent_app_type] => utility
[patent_app_number] => 10/693200
[patent_app_country] => US
[patent_app_date] => 2003-10-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/693200 | Method for manufacturing semiconductor device having porous structure with air-gaps | Oct 23, 2003 | Issued |
Array
(
[id] => 1005328
[patent_doc_number] => 06905922
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[patent_issue_date] => 2005-06-14
[patent_title] => 'Dual fully-silicided gate MOSFETs'
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[firstpage_image] =>[orig_patent_app_number] => 10678710
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/678710 | Dual fully-silicided gate MOSFETs | Oct 2, 2003 | Issued |
Array
(
[id] => 7278757
[patent_doc_number] => 20040061134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Semiconductor substrate with defects reduced or removed and method of manufacturing the same, and semiconductor device capable of bidirectionally retaining breakdown voltage and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/670331
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[firstpage_image] =>[orig_patent_app_number] => 10670331
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/670331 | SEMICONDUCTOR SUBSTRATE WITH DEFECTS REDUCED OR REMOVED AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE CAPABLE OF BIDIRECTIONALLY RETAINING BREAKDOWN VOLTAGE AND METHOD OF MANUFACTURING THE SAME | Sep 25, 2003 | Issued |
Array
(
[id] => 1126505
[patent_doc_number] => 06790720
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[patent_kind] => B1
[patent_issue_date] => 2004-09-14
[patent_title] => 'Method for fabricating a MOSFET and reducing line width of gate structure'
[patent_app_type] => B1
[patent_app_number] => 10/605360
[patent_app_country] => US
[patent_app_date] => 2003-09-25
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[pdf_file] => patents/06/790/06790720.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605360
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605360 | Method for fabricating a MOSFET and reducing line width of gate structure | Sep 24, 2003 | Issued |