CONTEST
Competed$7,000
This contest is closed.
Problem
Patexia seeks prior art for US Patent 7,779,205 (‘205) which allegedly describes a multiprocessor system comprised of a plurality of processors, a system bus, and a main system memory. Each processor is connected to a respective cache memory and in turn each cache memory is connected to the system bus. One processor is also connected directly to a non-cache local memory which has two ports; the first connected to the associated processor and the second to the system bus. A plurality of the remaining processors have access to the non-cache local memory via the system bus. The coherent caching of local memory data can take place by following these steps (Figure 1):
Figure 1: Coherent caching of local memory data
- Each processor is connected to a cache memory, which stores copies of data and instructions that are frequently used by the respective processors.
- Each cache memory is connected to the system bus.
- One processor is also connected to a non-cache local memory.
- The non-cache local memory has a first port for connection with the associated processor and a second port that is connected to the system bus allowing one or more of the other processors to access the non-cache local memory.
- First (Shared) and second (Invalid) status bits are assigned to each block within the non-cache local memory.
- The processor that is associated with the non-cache local memory checks the Shared and Invalid bits whenever the processor accesses the non-cache local memory.
- Read and write operations performed by the processor manipulate the data without impacting memory coherence by checking the status of the bits within the data block of the non-cache local memory that is associated with that processor.
Questions
- Was the source filed or published before November 24th, 2004?
- Does the source describe a multiprocessor system comprised of a plurality of processors, a system bus, and a main system memory? (20 points)
- Does the source describe one processor directly connected to a non-cache local memory? (30 points)
- Does the source describe a non-cache local memory that incorporates two ports; one connected directly to the first processor and another connected to the system bus? (10 points)
- Does the source describe a plurality of processors having access to the non-cache local memory via the system bus? (10 points)
- Does the source describe a non-cache local memory that is separate from the main system memory? (10 points)
- Does the source describe a non-cache local memory that is adapted to store information in data blocks? (10 points)
- Is each data block assigned a first status bit indicating whether or not the data block is shared, and a second status bit indicating whether or not the data block is invalid? (10 points)
Questions
# | Question | Value |
---|---|---|
1 | Was the source filed or published before November 24th, 2004? | 0 |
2 | Does the source describe a multiprocessor system comprised of a plurality of processors, a system bus, and a main system memory? (20 points) | 20 |
3 | Does the source describe one processor directly connected to a non-cache local memory? (30 points) | 30 |
4 | Does the source describe a non-cache local memory that incorporates two ports; one connected directly to the first processor and another connected to the system bus? (10 points) | 10 |
5 | Does the source describe a plurality of processors having access to the non-cache local memory via the system bus? (10 points) | 10 |
6 | Does the source describe a non-cache local memory that is separate from the main system memory? (10 points) | 10 |
7 | Does the source describe a non-cache local memory that is adapted to store information in data blocks? (10 points) | 10 |
8 | Is each data block assigned a first status bit indicating whether or not the data block is shared, and a second status bit indicating whether or not the data block is invalid? (10 points) | 10 |
Additional Notes
Contest Rules and Guidelines
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Known References
US5291442
US5590308
US5802577
US5832534
US6356983
US20030018859
US20060253655
EP0596636A2
Hennessy et al: "Computer Architecture a Quantitative Approach", Third Edition, 2003, Morgan Kaufmann Publishers, Chapter 5, pp. 389-512.