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Patexia seeks prior art for US Patent 8,681,164 (‘164), with a focus on claims 1, 6, 8, 9, 11, and 12. The patent allegedly describes a computing device with a memory bus that is attached to a main memory unit and has bandwidth sufficient to support a coupled decoder/encoder’s real-time decoding operation.
The entire system is described as having the following components:
- a central processing unit (CPU)
- a cache memory
- a core logic with a memory interface connected to the memory bus
- and a common bus to connect the CPU, the cache memory, and the core logic unit
Additionally, the system also includes:
- a decoder/encoder with a direct memory access (DMA) engine
- an arbiter
- a refresh logic unit
- a memory interface
- and an integrated circuit with all 4 components monolithically integrated together
Finally, the system also includes:
- a shared main memory unit
- and a memory bus to connect the main memory to the core logic unit’s memory interface and the memory interface on the integrated circuit
Using these memory interfaces, the memory bus can pass data:
- to the CPU by way of the core logic unit’s memory interface
- and to the decoder/encoder by way of memory interface on the integrated circuit
Additionally, some of these components have specific functionality available to them:
- the memory bus is described as having bandwidth greater than 2 times (2x) the data transferred to from the main memory to the decoder/encoder when real-time decoding is occurring
- the arbiter is described as being sensitive to main memory access requests from either the CPU or the decoder/encoder, and controls which component is accessing the main memory when multiple requests are received (or “arbitrates”)
- the DMA engine is described as controlling the data bursts between the decoder/encoder and the shared main memory
- the refresh logic unit is described as maintaining the contents of the main memory unit
Figure. Block diagram of the computing device.
- references filed or published before 08/26/1996
- patents or non-patent literature references
- no geographic restrictions for references
- no references allowed from the known references list
|Is the reference either a US patent filed, a foreign patent published, or a non-patent document published before August 26th, 1996?
|Does the reference describe a computing device with a central processing unit (CPU), a cache memory, and a core logic unit with a memory interface all interconnected by a common bus?
|Does the reference also describe a computing device with a decoder/encoder, an arbiter, a refresh logic unit, and a memory interface all on the same integrated circuit?
|Does the reference also describe the memory interfaces being connected to a memory bus in order to pass data from a shared main memory to the CPU via the core logic unit’s memory interface and to the decoder/encoder via the memory interface on the integrated circuit?
|Does the memory bus have a bandwidth larger than 2 times the amount of data transferred from the shared main memory to the decoder/encoder during real-time decoding?
|Does the arbiter on the integrated circuit serve to receive main memory access requests from the CPU and from the decoder/encoder, and to arbitrate requests to allow access?
|Does the decoder/encoder include a direct memory access (DMA) engine, also coupled to the integrated circuit’s memory interface, that is used to control the data bursts between the decoder/encoder and the shared main memory?
|Does the refresh logic unit on the integrated circuit serve to maintain the contents of the shared main memory?
This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.
+5 bonus points will be awarded for non-patent literature and for foreign language references.
This contest will close on Sunday, January 18th, 2015 at 11:59 PM PST and is subject to modified prize distribution awards:
- the top submission will be designated as a winner and receive $3,000
- the next scored 2 submissions will be designated as winners and receive $500 each
- the next scored submissions (to a maximum of 10) will be designated as runners up and receive a minimum of $100 each