Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4922043 [patent_doc_number] => 20080070358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/980603 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2468 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070358.pdf [firstpage_image] =>[orig_patent_app_number] => 11980603 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980603
Method of manufacturing semiconductor device having dual gate electrode Oct 30, 2007 Issued
Array ( [id] => 581996 [patent_doc_number] => 07449392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Semiconductor device capable of threshold voltage adjustment by applying an external voltage' [patent_app_type] => utility [patent_app_number] => 11/877820 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2973 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449392.pdf [firstpage_image] =>[orig_patent_app_number] => 11877820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877820
Semiconductor device capable of threshold voltage adjustment by applying an external voltage Oct 23, 2007 Issued
Array ( [id] => 4915718 [patent_doc_number] => 20080096318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'METHOD OF CONNECTING CARRIER TAPES AND TCP MOUNTING APPARATUS USED THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/874467 [patent_app_country] => US [patent_app_date] => 2007-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14661 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096318.pdf [firstpage_image] =>[orig_patent_app_number] => 11874467 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874467
METHOD OF CONNECTING CARRIER TAPES AND TCP MOUNTING APPARATUS USED THEREFOR Oct 17, 2007 Abandoned
Array ( [id] => 4514895 [patent_doc_number] => 07932123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Release strategies for making transferable semiconductor structures, devices and device components' [patent_app_type] => utility [patent_app_number] => 11/858788 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 77 [patent_no_of_words] => 18515 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932123.pdf [firstpage_image] =>[orig_patent_app_number] => 11858788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858788
Release strategies for making transferable semiconductor structures, devices and device components Sep 19, 2007 Issued
Array ( [id] => 33264 [patent_doc_number] => 07786010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method for forming a thin layer on semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 11/856908 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9117 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/786/07786010.pdf [firstpage_image] =>[orig_patent_app_number] => 11856908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856908
Method for forming a thin layer on semiconductor substrates Sep 17, 2007 Issued
11/846439 Semiconductor integrated circuit device and the process of the same Aug 27, 2007 Abandoned
Array ( [id] => 247384 [patent_doc_number] => 07586138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Image sensor and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/833237 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2447 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/586/07586138.pdf [firstpage_image] =>[orig_patent_app_number] => 11833237 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833237
Image sensor and method of forming the same Aug 2, 2007 Issued
Array ( [id] => 4578843 [patent_doc_number] => 07825508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Multi-die DC-DC buck power converter with efficient packaging' [patent_app_type] => utility [patent_app_number] => 11/830996 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4092 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825508.pdf [firstpage_image] =>[orig_patent_app_number] => 11830996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830996
Multi-die DC-DC buck power converter with efficient packaging Jul 30, 2007 Issued
Array ( [id] => 5028470 [patent_doc_number] => 20070269917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'ELECTRONIC DEVICES HAVING A LAYER OVERLYING AN EDGE OF A DIFFERENT LAYER AND A PROCESS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/830530 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12909 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20070269917.pdf [firstpage_image] =>[orig_patent_app_number] => 11830530 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830530
Electronic devices having a layer overlying an edge of a different layer and a process for forming the same Jul 29, 2007 Issued
Array ( [id] => 264130 [patent_doc_number] => 07569897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Low-capacitance contact for long gate-length devices with small contacted pitch' [patent_app_type] => utility [patent_app_number] => 11/767635 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6992 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/569/07569897.pdf [firstpage_image] =>[orig_patent_app_number] => 11767635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767635
Low-capacitance contact for long gate-length devices with small contacted pitch Jun 24, 2007 Issued
Array ( [id] => 820892 [patent_doc_number] => 07408226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Electronic card with protection against aerial discharge' [patent_app_type] => utility [patent_app_number] => 11/757867 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 73 [patent_no_of_words] => 16015 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408226.pdf [firstpage_image] =>[orig_patent_app_number] => 11757867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/757867
Electronic card with protection against aerial discharge Jun 3, 2007 Issued
Array ( [id] => 4711246 [patent_doc_number] => 20080299772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Methods of fabricating electronic devices using direct copper plating' [patent_app_type] => utility [patent_app_number] => 11/810287 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6040 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299772.pdf [firstpage_image] =>[orig_patent_app_number] => 11810287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810287
Methods of fabricating electronic devices using direct copper plating Jun 3, 2007 Issued
Array ( [id] => 4919369 [patent_doc_number] => 20080067681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/756853 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067681.pdf [firstpage_image] =>[orig_patent_app_number] => 11756853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756853
INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF May 31, 2007 Abandoned
Array ( [id] => 4749297 [patent_doc_number] => 20080157368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'MULTI-LAYERED METAL LINE OF SEMICONDUCTOR DEVICE HAVING EXCELLENT DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/755814 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2422 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157368.pdf [firstpage_image] =>[orig_patent_app_number] => 11755814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/755814
Multi-layered metal line of semiconductor device having excellent diffusion barrier and method for forming the same May 30, 2007 Issued
Array ( [id] => 4711224 [patent_doc_number] => 20080299750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'MULTIPLE MILLISECOND ANNEALS FOR SEMICONDUCTOR DEVICE FABRICATION' [patent_app_type] => utility [patent_app_number] => 11/756197 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299750.pdf [firstpage_image] =>[orig_patent_app_number] => 11756197 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756197
Multiple millisecond anneals for semiconductor device fabrication May 30, 2007 Issued
Array ( [id] => 4624221 [patent_doc_number] => 08003517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Method for forming interconnects for 3-D applications' [patent_app_type] => utility [patent_app_number] => 11/807777 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2601 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003517.pdf [firstpage_image] =>[orig_patent_app_number] => 11807777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/807777
Method for forming interconnects for 3-D applications May 28, 2007 Issued
Array ( [id] => 319088 [patent_doc_number] => 07521800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Solder pad and method of making the same' [patent_app_type] => utility [patent_app_number] => 11/752934 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 4819 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/521/07521800.pdf [firstpage_image] =>[orig_patent_app_number] => 11752934 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752934
Solder pad and method of making the same May 23, 2007 Issued
Array ( [id] => 4775961 [patent_doc_number] => 20080283959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Tapered through-silicon via structure' [patent_app_type] => utility [patent_app_number] => 11/803783 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2997 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20080283959.pdf [firstpage_image] =>[orig_patent_app_number] => 11803783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/803783
Tapered through-silicon via structure May 15, 2007 Issued
Array ( [id] => 282204 [patent_doc_number] => 07554205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Flip-chip type semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/798224 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 12065 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554205.pdf [firstpage_image] =>[orig_patent_app_number] => 11798224 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798224
Flip-chip type semiconductor device May 10, 2007 Issued
Array ( [id] => 5256728 [patent_doc_number] => 20070210360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'CMOS imager with selectively silicided gate' [patent_app_type] => utility [patent_app_number] => 11/797870 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7467 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210360.pdf [firstpage_image] =>[orig_patent_app_number] => 11797870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797870
CMOS imager with selectively silicided gate May 7, 2007 Issued
Menu