Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5171978
[patent_doc_number] => 20070072411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-29
[patent_title] => 'Method for forming metal line in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/448942
[patent_app_country] => US
[patent_app_date] => 2006-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2122
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0072/20070072411.pdf
[firstpage_image] =>[orig_patent_app_number] => 11448942
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/448942 | Method for forming metal line in semiconductor device | Jun 7, 2006 | Abandoned |
Array
(
[id] => 210367
[patent_doc_number] => 07625766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-01
[patent_title] => 'Methods of forming carbon nanotubes and methods of fabricating integrated circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/445708
[patent_app_country] => US
[patent_app_date] => 2006-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/625/07625766.pdf
[firstpage_image] =>[orig_patent_app_number] => 11445708
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/445708 | Methods of forming carbon nanotubes and methods of fabricating integrated circuitry | Jun 1, 2006 | Issued |
Array
(
[id] => 5171928
[patent_doc_number] => 20070072361
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-29
[patent_title] => 'METHOD OF REDUCING CURRENT LEAKAGE IN A METAL INSULATOR METAL SEMICONDUCTOR CAPACITOR AND SEMICONDUCTOR CAPACITOR THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/421771
[patent_app_country] => US
[patent_app_date] => 2006-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0072/20070072361.pdf
[firstpage_image] =>[orig_patent_app_number] => 11421771
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421771 | Method of reducing current leakage in a metal insulator metal semiconductor capacitor and semiconductor capacitor thereof | Jun 1, 2006 | Issued |
Array
(
[id] => 285893
[patent_doc_number] => 07550822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-23
[patent_title] => 'Dual-damascene metal wiring patterns for integrated circuit devices'
[patent_app_type] => utility
[patent_app_number] => 11/421202
[patent_app_country] => US
[patent_app_date] => 2006-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3140
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/550/07550822.pdf
[firstpage_image] =>[orig_patent_app_number] => 11421202
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421202 | Dual-damascene metal wiring patterns for integrated circuit devices | May 30, 2006 | Issued |
Array
(
[id] => 5141922
[patent_doc_number] => 20070004138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Method of manufacturing flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/440519
[patent_app_country] => US
[patent_app_date] => 2006-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1947
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20070004138.pdf
[firstpage_image] =>[orig_patent_app_number] => 11440519
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/440519 | Method of manufacturing flash memory device | May 24, 2006 | Issued |
Array
(
[id] => 5444280
[patent_doc_number] => 20090045506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'Cu-Mo SUBSTRATE AND METHOD FOR PRODUCING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/915201
[patent_app_country] => US
[patent_app_date] => 2006-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 11655
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[pdf_file] => publications/A1/0045/20090045506.pdf
[firstpage_image] =>[orig_patent_app_number] => 11915201
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/915201 | Cu-Mo substrate and method for producing same | May 22, 2006 | Issued |
Array
(
[id] => 151317
[patent_doc_number] => 07682888
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'Methods of forming NMOS/PMOS transistors with source/drains including strained materials'
[patent_app_type] => utility
[patent_app_number] => 11/435968
[patent_app_country] => US
[patent_app_date] => 2006-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 5105
[patent_no_of_claims] => 26
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/682/07682888.pdf
[firstpage_image] =>[orig_patent_app_number] => 11435968
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/435968 | Methods of forming NMOS/PMOS transistors with source/drains including strained materials | May 16, 2006 | Issued |
Array
(
[id] => 228794
[patent_doc_number] => 07601607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-13
[patent_title] => 'Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects'
[patent_app_type] => utility
[patent_app_number] => 11/434318
[patent_app_country] => US
[patent_app_date] => 2006-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3970
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/601/07601607.pdf
[firstpage_image] =>[orig_patent_app_number] => 11434318
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/434318 | Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects | May 14, 2006 | Issued |
Array
(
[id] => 5661577
[patent_doc_number] => 20060252173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Method for manufacturing photoelectric package having control chip'
[patent_app_type] => utility
[patent_app_number] => 11/416161
[patent_app_country] => US
[patent_app_date] => 2006-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2065
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20060252173.pdf
[firstpage_image] =>[orig_patent_app_number] => 11416161
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/416161 | Method for manufacturing photoelectric package having control chip | May 2, 2006 | Abandoned |
Array
(
[id] => 252638
[patent_doc_number] => 07579271
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-25
[patent_title] => 'Method for forming low dielectric constant fluorine-doped layers'
[patent_app_type] => utility
[patent_app_number] => 11/418501
[patent_app_country] => US
[patent_app_date] => 2006-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 5414
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[pdf_file] => patents/07/579/07579271.pdf
[firstpage_image] =>[orig_patent_app_number] => 11418501
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/418501 | Method for forming low dielectric constant fluorine-doped layers | May 2, 2006 | Issued |
Array
(
[id] => 267059
[patent_doc_number] => 07566584
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/417301
[patent_app_country] => US
[patent_app_date] => 2006-05-02
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[pdf_file] => patents/07/566/07566584.pdf
[firstpage_image] =>[orig_patent_app_number] => 11417301
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/417301 | Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method | May 1, 2006 | Issued |
Array
(
[id] => 7597686
[patent_doc_number] => 07618891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-17
[patent_title] => 'Method for forming self-aligned metal silicide contacts'
[patent_app_type] => utility
[patent_app_number] => 11/415922
[patent_app_country] => US
[patent_app_date] => 2006-05-01
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[pdf_file] => patents/07/618/07618891.pdf
[firstpage_image] =>[orig_patent_app_number] => 11415922
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/415922 | Method for forming self-aligned metal silicide contacts | Apr 30, 2006 | Issued |
Array
(
[id] => 5834783
[patent_doc_number] => 20060246614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Method for manufacturing gallium nitride-based semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/411142
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11411142
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/411142 | Method for manufacturing gallium nitride-based semiconductor device | Apr 25, 2006 | Abandoned |
Array
(
[id] => 5625504
[patent_doc_number] => 20060264009
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[patent_kind] => A1
[patent_issue_date] => 2006-11-23
[patent_title] => 'Method for significant reduction of dislocations for a very high A1 composition A1GaN layer'
[patent_app_type] => utility
[patent_app_number] => 11/411191
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[firstpage_image] =>[orig_patent_app_number] => 11411191
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/411191 | Method for significant reduction of dislocations for a very high A1 composition A1GaN layer | Apr 24, 2006 | Issued |
Array
(
[id] => 5210506
[patent_doc_number] => 20070249090
[patent_country] => US
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[patent_title] => 'Phase-change memory cell adapted to prevent over-etching or under-etching'
[patent_app_type] => utility
[patent_app_number] => 11/410262
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[firstpage_image] =>[orig_patent_app_number] => 11410262
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/410262 | Phase-change memory cell adapted to prevent over-etching or under-etching | Apr 23, 2006 | Abandoned |
Array
(
[id] => 4816900
[patent_doc_number] => 20080224159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-18
[patent_title] => 'Optical Element, Optoelectronic Component Comprising Said Element, and the Production Thereof'
[patent_app_type] => utility
[patent_app_number] => 11/912831
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/912831 | Optical Element, Optoelectronic Component Comprising Said Element, and the Production Thereof | Apr 17, 2006 | Abandoned |
Array
(
[id] => 813691
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[patent_country] => US
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[patent_issue_date] => 2008-08-19
[patent_title] => 'Method of edge bevel rinse'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/279561 | Method of edge bevel rinse | Apr 11, 2006 | Issued |
Array
(
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[patent_issue_date] => 2007-10-11
[patent_title] => 'SELF-ALIGNED BODY CONTACT FOR A SEMICONDCUTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'Method for integrating DMOS into sub-micron CMOS process'
[patent_app_type] => utility
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[pdf_file] => patents/07/544/07544558.pdf
[firstpage_image] =>[orig_patent_app_number] => 11373278
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/373278 | Method for integrating DMOS into sub-micron CMOS process | Mar 12, 2006 | Issued |
Array
(
[id] => 295981
[patent_doc_number] => 07541250
[patent_country] => US
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[patent_issue_date] => 2009-06-02
[patent_title] => 'Method for forming a self-aligned twin well region with simplified processing'
[patent_app_type] => utility
[patent_app_number] => 11/371258
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/371258 | Method for forming a self-aligned twin well region with simplified processing | Mar 6, 2006 | Issued |