Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14707421 [patent_doc_number] => 10381473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => High-electron-mobility transistor with buried interconnect [patent_app_type] => utility [patent_app_number] => 15/643328 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4456 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643328
High-electron-mobility transistor with buried interconnect Jul 5, 2017 Issued
Array ( [id] => 12141300 [patent_doc_number] => 20180019383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/643136 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6787 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643136 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643136
Semiconductor light-emitting device and method for manufacturing the same Jul 5, 2017 Issued
Array ( [id] => 15760315 [patent_doc_number] => 10622285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Semiconductor device with solders of different melting points and method of manufacturing [patent_app_type] => utility [patent_app_number] => 15/643159 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 17215 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643159
Semiconductor device with solders of different melting points and method of manufacturing Jul 5, 2017 Issued
Array ( [id] => 14738671 [patent_doc_number] => 10388746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => FET with buried gate structure [patent_app_type] => utility [patent_app_number] => 15/643343 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3832 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643343
FET with buried gate structure Jul 5, 2017 Issued
Array ( [id] => 12861625 [patent_doc_number] => 20180179049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => MEMS SENSORS WITH SELECTIVELY ADJUSTED DAMPING OF SUSPENSION [patent_app_type] => utility [patent_app_number] => 15/643174 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643174 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643174
MEMS sensors with selectively adjusted damping of suspension Jul 5, 2017 Issued
Array ( [id] => 12716920 [patent_doc_number] => 20180130806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/642394 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642394
Semiconductor device Jul 5, 2017 Issued
Array ( [id] => 14801225 [patent_doc_number] => 10403623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Gate networks having positive temperature coefficients of resistance (PTC) for semiconductor power conversion devices [patent_app_type] => utility [patent_app_number] => 15/643146 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9625 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643146 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643146
Gate networks having positive temperature coefficients of resistance (PTC) for semiconductor power conversion devices Jul 5, 2017 Issued
Array ( [id] => 12141291 [patent_doc_number] => 20180019374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/642142 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7352 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642142 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642142
Group III nitride semiconductor light-emitting device and production method therefor Jul 4, 2017 Issued
Array ( [id] => 11990247 [patent_doc_number] => 20170294402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'Bonding Package Components Through Plating' [patent_app_type] => utility [patent_app_number] => 15/632686 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632686
Bonding package components through plating Jun 25, 2017 Issued
Array ( [id] => 12141295 [patent_doc_number] => 20180019378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'Method For Fabricating High-Efficiency Light Emitting Diode Having Light Emitting Window Electrode Structure' [patent_app_type] => utility [patent_app_number] => 15/628195 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7360 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628195
Method for fabricating high-efficiency light emitting diode having light emitting window electrode structure Jun 19, 2017 Issued
Array ( [id] => 14429803 [patent_doc_number] => 10319715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Semiconductor devices including separate doped regions [patent_app_type] => utility [patent_app_number] => 15/627768 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9805 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627768
Semiconductor devices including separate doped regions Jun 19, 2017 Issued
Array ( [id] => 13808501 [patent_doc_number] => 10181519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Power semiconductor device [patent_app_type] => utility [patent_app_number] => 15/628362 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3569 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628362
Power semiconductor device Jun 19, 2017 Issued
Array ( [id] => 12127799 [patent_doc_number] => 20180011385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/628252 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628252
Display apparatus and method of manufacturing the same Jun 19, 2017 Issued
Array ( [id] => 13629817 [patent_doc_number] => 20180366461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => METHODS OF FORMING A RESISTOR STRUCTURE BETWEEN ADJACENT TRANSISTOR GATES ON AN INTEGRATED CIRCUIT PRODUCT AND THE RESULTING DEVICES [patent_app_type] => utility [patent_app_number] => 15/627835 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627835
Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices Jun 19, 2017 Issued
Array ( [id] => 11974857 [patent_doc_number] => 20170279011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'Method for Producing a Conversion Lamina and Conversion Lamina' [patent_app_type] => utility [patent_app_number] => 15/616830 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4555 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616830 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616830
Method for producing a conversion lamina and conversion lamina Jun 6, 2017 Issued
Array ( [id] => 11967065 [patent_doc_number] => 20170271219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SCANNING ACOUSTIC MICROSCOPE SENSOR ARRAY FOR CHIP-PACKAGING INTERACTION PACKAGE RELIABILITY MONITORING' [patent_app_type] => utility [patent_app_number] => 15/615148 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615148
Scanning acoustic microscope sensor array for chip-packaging interaction package reliability monitoring Jun 5, 2017 Issued
Array ( [id] => 12154670 [patent_doc_number] => 20180025934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/613780 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613780
Semiconductor integrated circuit device having electrostatic discharge protection circuit Jun 4, 2017 Issued
Array ( [id] => 13214855 [patent_doc_number] => 10121803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Semiconductor device having auxiliary patterns [patent_app_type] => utility [patent_app_number] => 15/600330 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2897 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600330 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600330
Semiconductor device having auxiliary patterns May 18, 2017 Issued
Array ( [id] => 11946132 [patent_doc_number] => 20170250283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 15/594436 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11765 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594436
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer May 11, 2017 Issued
Array ( [id] => 11949648 [patent_doc_number] => 20170253799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR NANOCRYSTALS, METHOD FOR COATING SEMICONDUCTOR NANOCRYSTALS, AND PRODUCTS INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 15/482411 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482411
Semiconductor nanocrystals, method for coating semiconductor nanocrystals, and products including same Apr 6, 2017 Issued
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