Search

Kevin P Shaver

Supervisory Patent Examiner (ID: 9936, Phone: (571)272-4720 , Office: P/3754 )

Most Active Art Unit
3104
Art Unit(s)
3754, 3752, 3732, 2899, 3736, 3104, 3108, 3101
Total Applications
1590
Issued Applications
1285
Pending Applications
77
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16951664 [patent_doc_number] => 20210210356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/142140 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142140
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jan 4, 2021 Pending
Array ( [id] => 16858365 [patent_doc_number] => 20210159110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/140972 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140972
3D SEMICONDUCTOR DEVICE AND STRUCTURE Jan 3, 2021 Pending
Array ( [id] => 18001060 [patent_doc_number] => 11502171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Leakage-free implantation-free ETSOI transistors [patent_app_type] => utility [patent_app_number] => 17/134695 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3501 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134695
Leakage-free implantation-free ETSOI transistors Dec 27, 2020 Issued
Array ( [id] => 17055916 [patent_doc_number] => 20210265350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/128656 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128656
SEMICONDUCTOR DEVICE AND METHOD Dec 20, 2020 Pending
Array ( [id] => 17040826 [patent_doc_number] => 20210257462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect Transistors [patent_app_type] => utility [patent_app_number] => 17/126594 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126594
Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect Transistors Dec 17, 2020 Pending
Array ( [id] => 17417041 [patent_doc_number] => 20220051945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => Embedded Stressors in Epitaxy Source/Drain Regions [patent_app_type] => utility [patent_app_number] => 17/124017 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124017
Embedded Stressors in Epitaxy Source/Drain Regions Dec 15, 2020 Pending
Array ( [id] => 18105600 [patent_doc_number] => 11545498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => OTP memory and method for making the same [patent_app_type] => utility [patent_app_number] => 17/111099 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5419 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 498 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111099
OTP memory and method for making the same Dec 2, 2020 Issued
Array ( [id] => 16715901 [patent_doc_number] => 20210083048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/107448 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107448
SEMICONDUCTOR DEVICE Nov 29, 2020 Pending
Array ( [id] => 17203501 [patent_doc_number] => 20210343596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SOURCE/DRAIN EPITAXIAL STRUCTURES FOR HIGH VOLTAGE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/107091 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107091
SOURCE/DRAIN EPITAXIAL STRUCTURES FOR HIGH VOLTAGE TRANSISTORS Nov 29, 2020 Pending
Array ( [id] => 16812256 [patent_doc_number] => 20210134811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => EMBEDDED NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/953643 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953643
EMBEDDED NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD OF THE SAME Nov 19, 2020 Abandoned
Array ( [id] => 18481166 [patent_doc_number] => 11694920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Substrate support device, thermal processing apparatus, substrate support method, and thermal processing method [patent_app_type] => utility [patent_app_number] => 17/079895 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 15270 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079895
Substrate support device, thermal processing apparatus, substrate support method, and thermal processing method Oct 25, 2020 Issued
Array ( [id] => 16624973 [patent_doc_number] => 20210043626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Integrated Circuit with a Gate Structure and Method Making the Same [patent_app_type] => utility [patent_app_number] => 17/080387 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080387
Integrated Circuit with a Gate Structure and Method Making the Same Oct 25, 2020 Pending
Array ( [id] => 18639480 [patent_doc_number] => 11764101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Susceptor for semiconductor substrate processing [patent_app_type] => utility [patent_app_number] => 17/075504 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10467 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075504
Susceptor for semiconductor substrate processing Oct 19, 2020 Issued
Array ( [id] => 17130495 [patent_doc_number] => 20210305264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS WITH ENHANCED FLOATING GATE TO FLOATING GATE CAPACITIVE COUPLING [patent_app_type] => utility [patent_app_number] => 17/069563 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069563 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069563
FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling Oct 12, 2020 Issued
Array ( [id] => 17486083 [patent_doc_number] => 20220093587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => INTEGRATED CIRCUIT LAYOUT AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/025917 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025917
INTEGRATED CIRCUIT LAYOUT AND METHOD THEREOF Sep 17, 2020 Pending
Array ( [id] => 16781906 [patent_doc_number] => 20210118985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CIRCUITS EMPLOYING ON-DIFFUSION (OD) EDGE (ODE) DUMMY GATE STRUCTURES IN CELL CIRCUIT WITH INCREASED GATE DIELECTRIC THICKNESS TO REDUCE LEAKAGE CURRENT [patent_app_type] => utility [patent_app_number] => 17/022338 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022338
CIRCUITS EMPLOYING ON-DIFFUSION (OD) EDGE (ODE) DUMMY GATE STRUCTURES IN CELL CIRCUIT WITH INCREASED GATE DIELECTRIC THICKNESS TO REDUCE LEAKAGE CURRENT Sep 15, 2020 Abandoned
Array ( [id] => 17772333 [patent_doc_number] => 11404284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Semiconductor device and formation thereof [patent_app_type] => utility [patent_app_number] => 17/019690 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019690
Semiconductor device and formation thereof Sep 13, 2020 Issued
Array ( [id] => 17448216 [patent_doc_number] => 20220068721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => High Voltage Device [patent_app_type] => utility [patent_app_number] => 17/008251 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008251
High Voltage Device Aug 30, 2020 Pending
Array ( [id] => 16509259 [patent_doc_number] => 20200388515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/001056 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001056
SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM Aug 23, 2020 Pending
Array ( [id] => 18464321 [patent_doc_number] => 11688615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => System and method for heating semiconductor wafers [patent_app_type] => utility [patent_app_number] => 16/997686 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997686
System and method for heating semiconductor wafers Aug 18, 2020 Issued
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