Patexia seeks prior art for US Patent 7,139,860 (US ‘860), which allegedly describes a method of allowing for multiple processors to be housed on the same chip, while allowing each processing core to be optimized to a particular protocol. This common on chip network accomplishes this by having a consistent port layer protocol to establish a common method to transfer data packets between processing cores and each core’s native logical layer protocol.

The on chip network (OCN) features a common physical layer interface that connects between a plurality of processor interfaces.

Each processor interface includes:

• a processing core connected to a bus gasket
• a bus gasket that is connected between the processing core and a port
• a port with an arbitration interface to connect to an arbiter and a data interface to send and receive data packets

The physical layer interface, common to the entire OCN, includes:

• an arbiter that is connected to the arbitration interfaces of every processor interface’s port
• an interconnect made up of a plurality of parallel buses that can create an instanced data path between the data interfaces of any processor interface’s port that is additionally isolated from any other instanced data path in order to decrease the number of clock cycles required for a transfer

Among these components on the OCN, there are two separate protocols:

• a plurality of logical layer protocols that allow each processing core to have a native protocol optimized to its function, with every processing core, associated bus gasket, and data packet configured to one of the logical layer protocols
• the consistent port interface protocol allows each port to communicate with the physical layer to transfer data between any processor interface, with each port, the arbiter, and the interconnect all configured to this protocol

In order to send a data packet between any two processor interfaces, the OCN takes the following steps:

• the sending processor interface port’s arbitration interface sends a transaction request to the arbiter to begin the transfer
• the arbiter sends an acknowledgement signal (ACK) back to the sending port’s arbitration interface to indicate it has clearance from the network to begin the transfer
• the arbiter then orders the interconnect to establish an instanced data path between the sending and receiving ports’ data interfaces
• the arbiter then sends a data enable signal to the receiving port’s arbitration interface to indicate an incoming data packet transfer
• finally, the sending port’s data interface sends the packet along the instanced data path to the receiving port’s data interface

Figure 1. Block Diagram of the Components at the Interface of a Common On Chip Network

Figure 2. Block Diagram of the Processor Interface to Physical Layer Interface to Processor Interface Junction

Questions

1. Was the reference filed or published before July 29th, 2002? (True/False)
2. Does the reference describe a network platform where multiple processing cores are networked on the same chip via a consistent port interface protocol to negotiate between each core’s logical layer protocol to transfer data between them? (10 points)
3. Does the reference describe the network platform being housed on an integrated circuit with a plurality of processor interfaces each including a processing core, a bus gasket, and a port with a separate arbitration and data interface; along with a common physical layer interface including an arbiter and an interconnect, all connected as shown in Figure 2? (15 points)
4. Within the same processor interface, are the processing core, bus gasket, and data packet all configured to operate to a selected logical layer protocol? (10 points)
5. In the entire network platform, are the arbiter, interconnect, and every port including each’s arbitration and data interfaces all configured to operate according to a consistent port interface protocol, independent of the logical layer protocols? (10 points)
6. Is the interconnect composed of a plurality of parallel bus units that allow the interconnect to establish an instanced data path that is optimized to go between any two processor interfaces, and is isolated from any other data paths instanced before or afterwards? (30 points)
7. Are data packets transferred between different processor interface by: (1) having the sending port’s arbitration interface send a transaction request to the arbiter which sends an acknowledge signal to confirm, (2) having the arbiter order the interconnect to establish an instanced data path, (3) having the arbiter send a data enable signal to the receiving port’s arbitration interface, and (4) having the sending port’s data interface sends the data packet along that established data path to the receiving port’s data interface? (25 points)